X40410V8-C datasheet(5/24 Pages) RENESAS

5 / 24 page

X40410, X40411, X40414, X40415

FN8116 Rev 0.00

Page 5 of 24

March 28, 2005

Resetting the VTRIPx Voltage

To reset a VTRIPx voltage, apply the programming volt-

age (Vp) to the WDO pin before a START condition is

set up on SDA. Next, issue on the SDA pin the Slave

Address A0h followed by the Byte Address 03h for

VTRIP1 and 0Bh for VTRIP2, followed by 00h for the Data

Byte in order to reset VTRIPx. The STOP bit following a

valid

write

operation

initiates

the

programming

sequence. Pin WDO must then be brought LOW to com-

plete the operation.

After being reset, the value of VTRIPx becomes a nomi-

nal value of 1.7V or lesser.

Note:

This operation does not corrupt the memory array.

CONTROL REGISTER

The Control Register provides the user a mechanism for

changing the Block Lock and Watchdog Timer settings.

The Block Lock and Watchdog Timer bits are nonvolatile

and do not change when power is removed.

The Control Register is accessed with a special preamble

in the slave byte (1011) and is located at address 1FFh. It

can only be modified by performing a byte write operation

directly to the address of the register and only one data

byte is allowed for each register write operation. Prior to

writing to the Control Register, the WEL and RWEL bits

must be set using a two step process, with the whole

sequence requiring 3 steps. See "Writing to the Control

Registers" on page 7.

The user must issue a stop, after sending this byte to the

WD0,

PUP1,

PUP0,

BP1,

and

BP0.

The

X40410/11/14/15 will not acknowledge any data bytes

written after the first byte is entered.

The state of the Control Register can be read at any time

by performing a random read at address 01Fh, using the

special preamble. Only one byte is read by each register

read operation. The master should supply a stop condi-

tion to be consistent with the bus protocol, but a stop is

not required to end this operation.

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to “1” prior to a write to the

Control Register.

Figure 4. Sample VTRIP Reset Circuit

543

PUP1 WD1 WD0

RWEL WEL PUP0

SOIC

VTRIP1

Adj.

RESET

4.7K

SDA

SCL

µC

Adjust

Run

V2FAIL

VTRIP2

Adj.

X4041x

X40410V8-C bảng dữ liệu(PDF) 5 Page - Renesas Technology Corp

X40410V8-C bảng dữ liệu(HTML) 5 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

bảng dữ liệu tải về

Link URL