Table 16. AC characteristics in Fast-mode plus

Symbol

Alt.

Parameter

Min.

Max.

Unit

fC

fSCL

Clock frequency

0

1

MHz

tCHCL

tHIGH

Clock pulse width high

260

-

ns

tCLCH

tLOW

Clock pulse width low

500

-

ns

tXH1XH2

tR

Input signal rise time

(1)

(1)

ns

tXL1XL2

tF

Input signal fall time

(1)

(1)

ns

tQL1QL2 (2)

tF

SDA (out) fall time

20(3)

120

ns

tDXCH

tSU:DAT

Data in setup time

50

-

ns

tCLDX

tHD:DAT

Data in hold time

0

-

ns

tCLQX (4)

tDH

Data out hold time

100

-

ns

tCLQV (5)

tAA

Clock low to next data valid (access time)

-

450

ns

tCHDL

tSU:STA

Start condition setup time

250

-

ns

tDLCL

tHD:STA

Start condition hold time

250

-

ns

tCHDH

tSU:STO

Stop condition setup time

250

-

ns

tDHDL

tBUF

Time between Stop condition and next Start condition

500

-

ns

tW

tWR

Write cycle time

-

5

ms

tNS (2)

-

Pulse width ignored (input filter on SCL and SDA)

-

50

ns

tWU(2)

-

Wake up time(6)

-

5

μs

1. There are no minimum or maximum values for the input signal rise and fall times. However, it is recommended by the I²C

specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when fC < 1 MHz.

2. Evaluated by characterization – Not tested in production.

3. With CL = 10 pF.

4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of

SDA.

5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming

that the Rbus × Cbus time constant is within the values specified in Figure 17.

6. Wake up time: Delay between the VCCmin stable and the first accepted command.

M24256X-F

DC and AC parameters

DS12380 - Rev 2

page 30/42