FS6407 datasheet(30/111 Pages) NXP

30 / 111 page

NXP Semiconductors

FS6407/FS6408

6.2.2

Select pin configuration

This phase detects the required voltage level to apply on VAUX and VCCA, according to the resistor value connected between the

SELECT pin and ground, (VAUX used) or between the SELECT pin and VPRE (VAUX not used). This mode is the equivalent mode seen

in the main state machine. Difference is in the fail-safe machine, this detection is used to internally set the UV/OV threshold on VCCA and

VAUX for the voltage supervision.

6.2.3

ABIST

Included in the fail-safe machine, the analog built-in self test (ABIST) verifies the correct functionality of the analog part of the device, like

the overvoltage and undervoltage detections of the voltage supervisor and the RTSTB and FS0B fail-safe outputs feedback (Table 9).

The ABIST is run at start-up and after each wake-up event when the device is in LPOFF mode.

6.2.4

Release RSTB

In this state, the device releases the RSTB pin.

6.2.5

INIT FS

This mode is automatically entered after the device is “powered on” and only if built-in self tests (Logic and Analog) have been passed

successfully. This INIT FS mode starts as soon as RSTB is released (means no “Activate RST” faults are present and no external reset

is requested). Faults leading to an “Activate RST” are described in Reset error counter.

In this mode, the device can be configured via the SPI within a maximum time of 256 ms, including first watchdog refresh. Some registers

can only be configured in this mode and is locked when leaving INIT FS mode (refer to Table 14 and Table 15). It is recommended, to

configure first the device before sending the first WD refresh. As soon as the first good watchdog refresh is sent by the MCU, the device

leaves this mode and goes into Normal WD mode.

6.2.6

Normal WD is running

In this mode, the device waits for a periodic watchdog refresh coming from the MCU, within a specific configured window timing.

Configuration of the watchdog window period can be set during INIT FS phase or in this mode. This mode is exited if there are consecutive

bad watchdog refreshes, if there is an external reset request, or if a fault occurs leading to an RSTB activation.

6.2.7

RST delay

When the reset pin is asserted low by the device, a delay runs, to release the RSTB, if there are no faults present. The reset low duration

time is configurable via the SPI in the INIT_ FSSM1 register, which is accessible for writing only in the INIT FS phase.

Table 9. Regulators and fail-safe pins checked during ABIST

Parameters

Overvoltage

Undervoltage

OK/NOK

VPRE

VCORE

VCCA

VAUX

IO_1 FB_Core Delta

RSTB

FS0B

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