STUW81300 datasheet(31/63 Pages) STMICROELECTRONICS

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DS11314 Rev 7

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STuW81300

Circuit description

7.11

RF output stage

The VCO output signal can be fed either to an RF output buffer or to a monolithic frequency

doubler, followed by a microwave output buffer.

The on-chip frequency multiplier allows the STuW81300 to cover a 7.7 GHz to 16 GHz

frequency range with high fundamental harmonic rejection.

The STuW81300 employs two different 100-ohm differential (50-ohm single-ended)

internally-matched broadband output stages, simplifying the design of the final application

and reducing the number of external components.

A first RF output stage buffer (pins RF1_OUTP, RF1_OUTN) supports the 1925 MHz to

4000 MHz (using the divider-by-2 path) and 3850 MHz to 8000 MHz frequency ranges

providing +6 dBm of output power @6 GHz into a 50-ohm single-ended resistive load.

The output stage buffer can be powered-down by software and/or hardware (pin PD_RF1).

A secondary microwave output stage (available on pins RF2_OUTP and RF2_OUTN) is

also provided to deliver the VCO frequency-doubled signal (7.7 GHz-to-16 GHz) and is able

to provide +4 dBm @12 GHz into a 50-ohm single-ended resistive load. This second output

stage can also be powered down by software and/or hardware (pin PD_RF2).

An RF mute function, which allows RF output stages to be kept OFF until the PLL achieves

lock status, can be selected by software.

The simultaneous use of both RF outputs (RF1 and RF2) is not supported. The user should

configure the power down bit of the RF output stage so as to avoid enabling both RF outputs

at the same time.

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