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STUW81300 bảng dữ liệu(PDF) 30 Page - STMicroelectronics |
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STUW81300 bảng dữ liệu(HTML) 30 Page - STMicroelectronics |
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30 / 63 page ![]() Circuit description STuW81300 30/63 DS11314 Rev 7 change, is performed in a very short time (~13 ms) minimizing the impact on the overall PLL switching time. Once the correct VCO and sub-band are selected the normal PLL operations are resumed. The VCO core can be supplied (pin#3) from 3.3 V to 4.5 V; the LDO_4V5 (programmable to 4.5 V and 3.3 V) is used for this purpose. Furthermore, the amplitude of oscillation, which trades current consumption with phase-noise performance is 3-bit programmable (ST4 Register, VCO_AMP bit). Section 7.16: STuW81300 register descriptions shows the allowed ranges of the oscillation amplitude for each available supply setting. In order to achieve the best phase-noise performance, the maximum allowed amplitude setting is recommended. VCO calibration auto-restart feature The VCO calibration auto-restart feature, once activated, allows the calibration procedure to be restarted when an event that moves the PLL into an unlock condition has occurred (trigger on ‘1’ to ‘0’ transition of the lock detector signal). This feature can be enabled through the EN_AUTOCAL bit (ST6 Register) and requires proper setting of the lock detector parameters (LD_PREC and LD_COUNT, ST4 Register), in order to avoid any unwanted transition of the lock detector signal during the transient time required by the PLL to lock the VCO at the desired frequency. Note: This feature is not available on product code STUW81300-1T, STUW81300-1TR. |
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