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9.10
INT2_CTRL (0Eh)
INT2 pin control register (R/W)
Each bit in this register enables a signal to be carried over INT2 when the MIPI I3CSM dynamic address is not
assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI when the MIPI I3CSM interface is used.
The output of the pad is the OR combination of the signals selected here and in register MD2_CFG (5Fh).
Table 38. INT2_CTRL register
0(1)
INT2_
CNT_BDR
INT2_
FIFO_FULL
INT2_
FIFO_OVR
INT2_
FIFO_TH
INT2_
DRDY_TEMP
INT2_
DRDY_G
INT2_
DRDY_XL
1. This bit must be set to 0 for the correct operation of the device.
Table 39. INT2_CTRL register description
INT2_CNT_BDR
Enables COUNTER_BDR_IA interrupt on INT2 pin.
INT2_FIFO_FULL
Enables FIFO full flag interrupt on INT2 pin.
INT2_FIFO_OVR
Enables FIFO overrun interrupt on INT2 pin.
INT2_FIFO_TH
Enables FIFO threshold interrupt on INT2 pin.
INT2_DRDY_TEMP
Enables temperature sensor data-ready interrupt on INT2 pin.
It can be also used to trigger an IBI when the MIPI I3CSM interface is used and INT2_ON_INT1 = 1 in
CTRL4_C (13h).
INT2_DRDY_G
Enables gyroscope data-ready interrupt on INT2 pin.
INT2_DRDY_XL
Enables accelerometer data-ready interrupt on INT2 pin.
9.11
WHO_AM_I (0Fh)
WHO_AM_I register (R). This is a read-only register. Its value is fixed at 6Bh.
Table 40. Who_Am_I register
0
1
1
0
1
0
1
1
ASM330LHB
INT2_CTRL (0Eh)
DS13773 - Rev 7
page 46/131



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