HC705P6AGRSSLASHD datasheet(93/134 Pages) NXP

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General Release Specification

Mask Option Register (MOR) $1EFF–$1F00

MC68HC705P6A — Rev. 1.0

General Release Specification

Mask Option Register (MOR)

LSBF — SIOP Least Significant Bit First

If the LSBF bit is set, the serial data to and from the SIOP will be

transferred least significant bit first. If the LSBF bit is clear, the serial

data to and from the SIOP will be transferred most significant bit first.

SPR0 and SPR1 — SIOP Clock Rate

The SPR0 and SPR1 bits determine the clock rate used to transfer the

serial data to and from the SIOP. The various clock rates available are

given in Table 11-1.

SWAIT — STOP Instruction Mode

Setting the SWAIT bit will prevent the STOP instruction from stopping

the on-board oscillator. Clearing the SWAIT bit will permit the STOP

instruction to stop the on-board oscillator and place the MCU in stop

mode. Executing the STOP instruction when SWAIT is set will place

the MCU in halt mode. See 3.5.1 STOP Instruction for additional

information.

SECURE — Security State1

If SECURE bit is set, the EPROM is locked.

PA(0:7)PU — Port A Pullups/Interrupt Enable/Disable

If any PA(0:7)PU is selected, that pullup/interrupt is enabled. The

interrupt sensitivity will be selected via the LEVEL bit in the same way

as the IRQ pin.

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the EPROM/OTPROM difficult for unauthorized users.

NOTE:

The port A pullup/interrupt function is NOT available on the ROM device,

MC68HC05P6.

Table 11-1. SIOP Clock Rate

SPR1

SPR0

SIOP Master Clock

fosc ÷ 64

fosc ÷ 32

fosc ÷ 16

fosc ÷ 8

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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