HC705P6AGRSSLASHD datasheet(43/134 Pages) NXP

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MC68HC705P6A — Rev. 1.0

General Release Specification

Interrupts

General Release Specification — MC68HC705P6A

Section 5. Interrupts

5.1 Contents

5.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

5.3

Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

5.3.1

Reset Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . .46

5.3.2

Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . .46

5.3.3

Hardware Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

5.3.3.1

External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . .46

5.3.3.2

Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .47

5.3.3.3

Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . .47

5.3.3.4

Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .47

5.2 Introduction

The MCU can be interrupted six different ways:

1. Non-maskable software interrupt instruction (SWI)

2. External asynchronous interrupt (IRQ)

3. Input capture interrupt (TIMER)

4. Output compare interrupt (TIMER)

5. Timer overflow interrupt (TIMER)

6. Port A interrupt (if selected via mask option register)

Interrupts cause the processor to save the register contents on the stack

and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike

RESET, hardware interrupts do not cause the current instruction

execution to be halted, but are considered pending until the current

instruction is completed.

When the current instruction is completed, the processor checks all

pending hardware interrupts. If interrupts are not masked (I bit in the

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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