68HC705SP7 datasheet(75/230 Pages) NXP

75 / 230 page

Operating Modes

Low-Power Modes

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

General Release Specification

Operating Modes

The following conditions restart the CPU bus clock and bring the MCU

out of wait mode:

•

An external interrupt signal on the IRQ/VPP pin — A high-to-low

transition on the IRQ/VPP pin loads the program counter with the

contents of locations $1FFA and $1FFB.

•

An external interrupt signal on a port A external interrupt pin — If

selected by PIRQ bit in the MOR, a low-to-high transition on a

PA3–PA0 pin loads the program counter with the contents of

locations $1FFA and $1FFB.

•

A core timer interrupt — A core timer overflow or a real-time

interrupt loads the program counter with the contents of locations

$1FF8 and $1FF9.

•

A programmable timer interrupt — A programmable timer interrupt

driven by an input capture, output compare, or timer overflow

loads the program counter with the contents of locations $1FF6

and $1FF7.

•

An SIOP interrupt — An SIOP interrupt driven by the completion

of transmitted or received 8-bit data loads the program counter

with the contents of locations $1FF4 and $1FF5.

•

An analog subsystem interrupt — An analog subsystem interrupt

driven by a voltage comparison loads the program counter with

the contents of locations $1FF2 and $1FF3.

•

A COP watchdog reset — A timeout of the COP watchdog resets

the MCU and loads the program counter with the contents of

locations $1FFE and $1FFF. Software can enable real time

interrupts so that the MCU can periodically exit the wait mode to

reset the COP watchdog.

•

An external reset — A logic zero on the RESET pin resets the

MCU and loads the program counter with the contents of locations

$1FFE and $1FFF.

When the MCU exits the wait mode there is no delay before code

executes like occurs when exiting the stop or halt modes.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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