Features
• Low-Cost, HC05 Core MCU in 20-Pin Package (MC68HC705JJ7)
or 28-Pin Package (MC68HC705JP7)
• 6160 Bytes of User EPROM (Including 16 Bytes of User Vectors)
• 224 Bytes of Low-Power User RAM (4 Transistors)
• 64 Bits of Personality EPROM (Serial Access)
• 16-Bit Programmable Timer with Input Capture and Output
Compare
• 15-Stage Core Timer Including 8-Bit Free-Running Counter
and 4-Stage Selectable Real-Time Interrupt Generator
• Simple Serial Input/Output Port (SIOP) with Interrupt Capability
• Two Voltage Comparators, One of Which Can be Combined with
the 16-Bit Programmable Timer to Create a 4-Channel, Single-
Slope A/D Converter
• Output of Voltage Comparator Can Drive Port Pin PB4 Directly
Under Software Control
• 14 I/O Lines (MC68HC705JJ7) or 22 I/O Lines (MC68HC705JP7)
Including High-Source/Sink Current Capability on 6 I/O Pins
(MC68HC705JJ7) or 14 I/O Pins (MC68HC705JP7)
• Programmable 8-Bit Mask Option Register (MOR) to Select Mask
Options Found in ROM-Based Versions
• MOR Selectable Software Programmable Pulldowns on All I/O
Pins and Keyboard Scan Interrupt on Four I/O Pins
• Software Mask and Request Bit for IRQ Interrupt with MOR
Selectable Sensitivity on IRQ Interrupt (Edge- and Level-Sensitive
or Edge-Only)
• On-Chip Oscillator with Device Option of Crystal/Ceramic
Resonator or RC Operation and MOR Selectable Shunt Resistor,
Approximately 2 MW
• Internal Oscillator for Lower-Power Operation, Approximately
100 kHz (500 kHz Selected as Device Option)
• EPROM Security Bit1 to Aid in Locking Out Access to
Programmable EPROM array
• MOR Selectable (COP) Watchdog System
• Power-Saving Stop and Wait Mode Instructions (MOR Selectable
STOP Conversion to Halt and Option for Fast 16-Cycle Restart,
and Power-On Reset)
• On-Chip Temperature Measurement Diode
• MOR Selectable Low-Voltage Inhibit to Reset CPU in Low-Voltage
Conditions
• Illegal Address Reset
• Internal Steering Diode and Pullup Device on RESET Pin to VDD