68HC705JB2 datasheet(41/128 Pages) NXP

41 / 128 page

August 28, 1998

GENERAL RELEASE SPECIFICATION

RESETS

REV 1.1

5-3

5.2.3 Illegal Address Reset (ILADR)

The internal ILADR reset is generated when an instruction opcode fetch occurs

from an address which is not implemented in the RAM ($0080 - $00FF) nor ROM

($1600-$1FFF). The ILADR will generate the RST signal which will reset the CPU

and other peripherals. If any other reset function is active at the end of the ILADR

reset signal, the RST signal will remain in the reset condition until the other reset

condition(s) end. Notice that ILADR also forces the RESET pin low

5.2.4 Low Voltage Reset (LVR)

The internal LVR reset is generated when VDD falls below the speciﬁed LVR

trigger value VLVR for at least one tCYC. In typical applications, the power supply

decoupling circuit will eliminate negative-going voltage glitches of less than one

tCYC. This reset will hold the MCU in the reset state until VDD rises above VLVR.

Whenever VDD is above VLVR and below 4.2V, the MCU is guaranteed to operate

although not within speciﬁcation. The output from the LVR is connected directly to

the internal reset circuitry and also forces the RESET pin low. The internal reset

will be removed once the power supply voltage rises above VLVR, at which time a

normal power-on-reset sequence occurs. LVR function will still be active during

Stop or Suspend mode.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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