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M95256-R bảng dữ liệu(PDF) 15 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  256-Kbit serial SPI bus EEPROM with high-speed clock
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6.3.4
SRWD bit
The Status register Write Disable (SRWD) bit is operated in conjunction with the Write protect (W) signal. The
Status register Write Disable (SRWD) bit and Write protect (W) signal enable the device to be put in the Hardware
Protected mode (when the Status register Write Disable (SRWD) bit is set to 1, and Write protect (W) is driven
low). In this mode, the non-volatile bits of the Status register (SRWD, BP1, BP0) become read-only bits and the
Write Status register (WRSR) instruction is no longer accepted for execution.
Table 6. Status register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL
WIP
Status register Write protect
Block protect bits
Write enable latch bit
Write in progress bit
M95256-W M95256-R M95256-DF
Read Status register (RDSR)
DS4712 - Rev 22
page 15/51



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