FXPS7115D4S datasheet(40/74 Pages) NXP

40 / 74 page

NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.8 SPI Configuration Control Register (SPI_CFG, Address 3Dh)

In SPI mode, the SPI configuration control register is a user programmed read/write

in the read/write array error detection. This register is readable and writable in SPI mode

or I2C mode

Bit

Symbol

reserved

DATASIZE

SPI_CRC_LEN[1:0]

SPICRCSEED[3:0]

Factory default

Access

R/W

Table 58. SPI_CFG Register (address 3Dh) bit allocation

7.7.8.1 SPI Data Field Size (DATASIZE)

The SPI data field size bit controls the size of the SPI data field as shown in Table 59.

DATASIZE

SPI Data Field Size

12-Bits

16-Bits

Table 59. DATASIZE Bit Definition

7.7.8.2 SPI CRC Length and Seed Bits

The SPI_CRC_LEN[1:0] bits select the CRC length for SPI Mode as shown in the table

below. The SPI CRC seed bits contain the seed used for the SPI Mode. The default SPI

CRC is an 8-bit. When the SPI_CRC_LEN[1:0] bits are set to a non-zero value using

a Register Write command, the SPI CRC changes as defined in the table. The new

polynomial value is enabled for both MISO and MOSI on the next SPI Mode command.

The default seed (SPICRCSEED[3:0] = 0h) is FFh for an 8-bit CRC. When the value

is changed to a non-zero value using a Register Write command, the SPI CRC seed

changes to the value programmed as shown in the table. The new seed value is enabled

for both MISO and MOSI on the next SPI Mode command.

SPI_CRC_LEN[1:0]

SPICRCSEED

CRC Polynomial

CRC Seed

x8 + x5 + x3 + x2 + x + 1

1111, 1111

non-zero

x8 + x5 + x3 + x2 + x + 1

0000, SPICRCSEED[3:0]

x4 + 1

1010

non-zero

x4 + 1

SPICRCSEED[3:0]

x3 + x + 1

111

non-zero

x3 + x + 1

SPICRCSEED[2:0]

x3 + x + 1

111

non-zero

x3 + x + 1

SPICRCSEED[2:0]

Table 60. SPI CRC Definition

7.7.9 WHO_AM_I - who am I register (address 3Eh)

The WHO_AM_I register is a user programmed read/write register that contains the

unique product identifier. This register is included in the read/write array error detection.

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 9 August 2022

40 / 74

FXPS7115D4S bảng dữ liệu(PDF) 40 Page - NXP Semiconductors

FXPS7115D4S bảng dữ liệu(HTML) 40 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

bảng dữ liệu tải về

Link URL