FXPS7115D4S datasheet(36/74 Pages) NXP

36 / 74 page

NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

RESET[0]

RESET[1]

Effect

No effect

Device RESET

Table 48. Device reset command sequence

The response to a register write returns the new register value, including the values

written to the RESET[1:0] bits. After the third register write command, the device initiates

a reset and therefore does not transmit a response to this command or an acknowledge

in I2C mode. The response to a register read returns '00' for RESET[1:0] and terminates

the reset sequence. The reset control bits are not included in the read/write array error

detection.

7.7.5 WRITE_OTP_EN – write OTP enable register (address 11h)

The write OTP enable register is a user programmed read/write register that allows the

user to write the contents of the user programmed OTP array mirror registers to the OTP

registers. This register is included in the user read/write array error detection.

This register is readable and writable in SPI and I2C modes.

Bit

Name

UOTP_WR_INIT

Reserved

EX_COMMTYPE

EX_PADDR

UOTP_REGION[1:0]

Access

R/W

Reset

Table 49. WRITE_OTP_EN – write OTP enable register – (address 11h) bit allocation

the mirror register contents for the OTP array, not the actual OTP registers. To copy the

values to the actual OTP registers, a write must be executed to the WRITE_OTP_EN

EX_COMMTYPE, and the EX_PADDR bits in the command determine which region of

OTP is written to as shown in Table 50.

EX_COMMTYPE EX_PADDR

UOTP_REGION[1] UOTP_REGION[0] OTP write operation

Special conditions

Write the current contents of the UF0 registers to OTP

—

Write the current contents of the UF1 registers to OTP

—

Reserved for future use.

—

Reserved for future use.

—

Reserved for future use.

—

Write the current contents of the UF2 registers to OTP.

Excluding LPF. LPF defaults to 1000

Hz at POR.

Reserved for future use

—

Table 50. Writes for OTP registers

The UF0 and UF1 user OTP regions as well as the NXP programmed F OTP regions

share common mirror registers. For this reason, writes to the OTP for each region must

be completed independently according to the procedure below.

Once a region is written using the OTP Write sequence, the LOCK_Uxxx bit in the

appropriate CRC_xxx register is automatically set, locking the array from future writes.

Once a region is locked, an error detection is activated to detect changes to the register

values. Register values in the UF2 region can be overwritten using register write

commands, but no new values can be written to the OTP.

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 9 August 2022

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