WM8770 datasheet(22/52 Pages) WOLFSON

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WM8770

Production Data

PD Rev 4.1 June 2005

LEFT JUSTIFIED MODE

In left justified mode, the MSB of DIN1/2/3/4 is sampled by the WM8770 on the first rising edge of

BCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on

the same falling edge of BCLK as ADCLRC and may be sampled on the rising edge of BCLK.

ADCLRC and DACLRC are high during the left samples and low during the right samples (Figure 14).

Figure 14 Left Justified Mode Timing Diagram

RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN1/2/3/4 is sampled by the WM8770 on the rising edge of BCLK

preceding a DACLRC transition. The LSB of the ADC data is output on DOUT and changes on the

falling edge of BCLK preceding a ADCLRC transition and may be sampled on the rising edge of

BCLK. ADCLRC and DACLRC are high during the left samples and low during the right samples

(Figure 15).

Figure 15 Right Justified Mode Timing Diagram

2S MODE

In I

2S mode, the MSB of DIN1/2/3/4 is sampled by the WM8770 on the second rising edge of BCLK

following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the

first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge of

BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples.

Figure 16 I

2S Mode Timing Diagram

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DIN1/2/3/4/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DIN1/2/3/4/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DIN1/2/3/4/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

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