ES9218PC datasheet(12/101 Pages) ESS

12 / 101 page

ES9218P Datasheet

December 6, 2018

CONFIDENTIAL ADVANCE INFORMATION 1.8

ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801

Master Mode

The DAC can be configured for master mode operation using Register 10: Master Mode and Sync Configuration (0x0A).

Register 1: Input selection (0x01) input_select must also be set to either DSD or Serial mode. Auto Select will not work correctly in master mode.

DATA_CLK frequency can be configured using one of the following methods:

1. Set the desired master_div in Register 10: Master Mode and Sync Configuration (0x0A)

2. Use NCO mode to set CLK/FSR ratio with Register 34-37: Programmable NCO (0x22 - 0x25). When NCO mode is enabled it has

precedence and the master_div setting will be ignored.

An available GPIO pin can be configured to output CLK using Register 8: GPIO1-2 Configuration (0x08). GPIO1 is recommended for this purpose

since GPIO2 is used to control Low Power Bypass mode.

Contact your local FAE for DoP master mode support.

SLAVE PCM MODE

BCK(Bit Clock)

LRCK(Frame Clock)

SIN(Serial PCM Data)

DATA_CLK

DATA1

DATA2

MASTER PCM MODE

BCK(Bit Clock)

LRCK(Frame Clock)

SIN(Serial PCM Data)

DATA_CLK

DATA1

DATA2

MCLK(Master Clock)

GPIO1

SLAVE DSD MODE

DSD DATA_CLK

DSD DATA1 (L)

DSD DATA2 (R)

DATA_CLK

DATA1

DATA2

MASTER DSD MODE

DSD DATA_CLK

DSD DATA1 (L)

DSD DATA2 (R)

DATA_CLK

DATA1

DATA2

MCLK (Master Clock)

GPIO1

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