công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

ES9218PC bảng dữ liệu(PDF) 60 Page - ESS Technology,Inc

tên linh kiện ES9218PC
Giải thích chi tiết về linh kiện  32-bit Stereo Low Power DAC with Headphone Amplifier, Analog Volume Control, and Output Switch
PDF  101 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  ESS [ESS Technology,Inc]
Trang chủ  http://www.esstech.com
Logo ESS - ESS Technology,Inc

ES9218PC bảng dữ liệu(HTML) 60 Page - ESS Technology,Inc

Back Button ES9218PC Datasheet HTML 56Page - ESS Technology,Inc ES9218PC Datasheet HTML 57Page - ESS Technology,Inc ES9218PC Datasheet HTML 58Page - ESS Technology,Inc ES9218PC Datasheet HTML 59Page - ESS Technology,Inc ES9218PC Datasheet HTML 60Page - ESS Technology,Inc ES9218PC Datasheet HTML 61Page - ESS Technology,Inc ES9218PC Datasheet HTML 62Page - ESS Technology,Inc ES9218PC Datasheet HTML 63Page - ESS Technology,Inc ES9218PC Datasheet HTML 64Page - ESS Technology,Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 60 / 101 page
background image
ES9218P Datasheet
December 6, 2018
CONFIDENTIAL ADVANCE INFORMATION 1.8
ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA Tel (408) 643-8800 • Fax (408) 643-8801
60
Register 26: Charge Pump Soft Start Delay (0x1A)
Bits
[7:0]
Mnemonic
cp_ss_delay
Default
8’d98
Bit
Mnemonic
Description
[7:0]
cp_ss_delay
Configures the delay between the weak charge pump enable and the strong charge pump enable. This
delay is to limit the inrush currents of the strong charge pump when powering up.
This relationship is not exact because chargepump clock frequency is not guaranteed to be exactly equal
to XI(MCLK). It is automatically adjusted to undo the effects of clock gearing. The result is that the
chargepump clock rate remains constant with respect to XI(MCLK) even when CLK changes but only to
within the truncation error of the chargepump clock divider.
delay(s) ≈
256 ∗ cp_ss_delay
fMCLK
Example: For the default register setting if XI(MCLK) = 25MHz, delay ≈ 1ms.
See System Clock XI(MCLK) for the relationship between XI(MCLK) and CLK.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com