COM90C66 datasheet(71/76 Pages) SMSC

tên linh kiện	COM90C66

Giải thích chi tiết về linh kiện	ARCNET Controller/Transceiver with AT Interface and On-Chip RAM

PDF	76 Pages

Scroll/Zoom	100%

nhà sản xuất	SMSC [SMSC Corporation]

Trang chủ	http://www.smsc.com

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FIGURE 15 - READ RAM CYCLE

nMEMR High to nTOPH, nTOPL High

Parameter

Address, nSBHE Set Up to BALE Low *

Address, nSBHE Hold after BALE Low *

Address, nSBHE Set Up to nMEMR Low

nMEMR Low to Valid Data

nMEMR Low to nTOPH, nTOPL Low

min

typ

max

units

nMEMR High to Data High Impedance

nMEMR High to BALE High (Next Address)

A19-A17 to nMEMCS16 Low (Unlatched) (128K RAM Decode)

A19-A11 to nMEMCS16 Low (Latched) (2K RAM Decode)

Address, nSBHE invalid to nMEMCS16 High

t10

t11

A0-A19

VALID DATA

VALID

t10

BALE

nMEMR

D0-D7

nTOPL

nTOPH,

nMEMCS16

(Unlatched)

nMEMCS16

(Latched)

D0-D15

nSBHE

t11

t2***

For latched addresses, t1 and t2 do not apply. Please refer to Figure 21 for Latched Address

Mode

130ns minimum inactive time on consective memory reads from the COM90C66.

For Revision D devices, if BALE is tied high, then Address, nSBHE must be held for 20nsec

after nMEMR Low.

***

Modified Version of Page 50 for Rev. D COM90C66 Only.

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