L9300 datasheet(157/182 Pages) STMICROELECTRONICS

157 / 182 page

17.1.2

Power supply electrical characteristics

5.5V ≤ VBATP≤ 19V; -40°C ≤ Tj ≤ 175°C unless otherwise noticed. All voltages refer to GND pin.

Table 62. Power supply electrical characteristics

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

VDD3-4 monitor

t_an_chop_clock

analog chopping period

Guaranteed by scan

µs

17.1.3

Power supply error handling

Table 63. Power supply error handling

Type of error

Detection condition

Action

Clear SPI

flag

Restart condition

VDD3

VDD3 under

voltage self test

fail

On state, enabled through SPI bit

VDDx UV/OV Self Test Enable (16)

in SERVENA register

Same as regulator fault detection,

with additional VDDx OV/UV Self

Test bit (10) set in SERVFLT register

Clear on

read

Same as functional, self

test enable to be re-

enabled

VDD3 over

voltage self test

fail

On state, enabled through SPI bit

VDDx UV/OV Self Test Enable (16)

in SERVENA register

Same as regulator fault detection,

with additional VDDx OV/UV Self

Test bit (10) set in SERVFLT register

Clear on

read

Same as functional, self

test enable to be re-

enabled

VDD4

VDD4 under

voltage self test

fail

On state, enabled through SPI bit

VDDx UV/OV Self Test Enable (16)

in SERVENA register

Same as regulator fault detection,

with additional VDDx OV/UV Self

Test bit (10) set in SERVFLT register

Clear on

read

Same as functional, self

test enable to be re-

enabled

VDD4 over

voltage self test

fail

On state, enabled through SPI bit

VDDx UV/OV Self Test Enable (16)

in SERVENA register

Same as regulator fault detection,

with additional VDDx OV/UV Self

Test bit (10) set in SERVFLT register

Clear on

read

Same as functional, self

test enable to be re-

enabled

17.2

Internal supply monitor

17.2.1

Reference Oscillator

A second trimmed 16 MHz oscillator runs in parallel with the main one and it is used to monitor its accuracy, if a

frequency drift on any of the two oscillators happens a power down sequence is triggered with consequent reset

generation and channel disabled; safe state lasts until the fail is recovered or the device is restarted by toggling of

the wake pin. After system restart, if the fail is still present, the device enters the safe state condition again. Basic

implementation of clock monitor is shown in the following figure.

L9300

Internal supply monitor

DS12258 - Rev 4

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