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R5F51406BDFK30 bảng dữ liệu(PDF) 10 Page - Renesas Technology Corp |
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R5F51406BDFK30 bảng dữ liệu(HTML) 10 Page - Renesas Technology Corp |
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10 / 118 page ![]() R01DS0379EJ0110 Rev.1.10 Page 10 of 118 Apr 20, 2022 RX140 Group 1. Overview 1.3 Block Diagram Figure 1.2 shows a block diagram. Figure 1.2 Block Diagram Clock generation circuit RX CPU RAM ROM Port 1 Port 2 Port 4 Port 5 8-bit D/A converter × 2 channels SCIk x 2 channels DOC E2 DataFlash RTCB x 1 channel MTU2a x 6 channels 12-bit A/D converter × 18 channels TMRa × 2 channels (Unit 1) CRC DTCb ICUb CAC IWDTa Port A Port B Port C Port D RSPIc x 1 channel Port 3 Temperature sensor Port E Port G Port H Comparator B POE2a TMRa × 2 channels (Unit 0) SCIh x 1 channel CMT × 2 channels (Unit 0) RIICa × 1 channel Port 0 ELC LPTa RSCAN CAC CTSU2SL, CTSU2L Port J RNGA AESA SCIg x 3 channels ICUb: Interrupt controller DTCb: Data transfer controller IWDTa: Independent watchdog timer ELC: Event link controller CRC: CRC (cyclic redundancy check) calculator SCIk, SCIg, SCIh: Serial communications interface RSPIc: Serial peripheral interface RIICa: I2C bus interface MTU2a: Multi-function timer pulse unit 2 POE2a: Port output enable 2 RTCB: Realtime clock DOC: Data operation circuit CAC: Clock frequency accuracy measurement circuit CTSU2SL, CTSU2L: Capacitive touch sensing unit TMRa: 8-bit timer LPTa: Low power timer RSCAN: CAN module AESA: Advanced encryption standard hardware accelerator RNGA: True-random number generator Note: Available functions depend on the product. |
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