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5 / 118 page  R01DS0379EJ0110 Rev.1.10 Page 5 of 118 Apr 20, 2022 RX140 Group 1. Overview Note 1. The 12-bit A/D converter has 17 external input channels and a single internal input channel. For details, refer to section 35, 12- Bit A/D Converter (S12ADE) in the User’s Manual: Hardware. Capacitive touch sensing unit (CTSU2SL, CTSU2L) • CTSU2L Self-capacitance method: A single pin configures a single key, supporting up to 36 keys Mutual capacitance method: Matrix configuration with 8 × 8, supporting up to 64 keys • CTSU2SL (The following functions are added to CTSU2L) Automatic correction Automatic judgment Data operation circuit (DOC) Comparison, addition, and subtraction of 16-bit data Unique ID 32-byte ID code for the MCU Encryption function Advanced encryption standard hardware accelerator (AESA) • Key lengths: 128 and 256 bits • Support for ECB, CBC, and CTR operating modes • Speed of calculations: 128-bit key length in 176 cycles 256-bit key length in 240 cycles • Compliant with FIPS PUB 197 True random number generator (RNGA) • Length of random numbers: 32 bits • Generation of random-number-generated interrupts after a number is generated Power supply voltages/Operating frequencies VCC = 1.8 to 5.5 V: 48 MHz Operating temperature range D version: –40 to +85°C, G version: –40 to +105°C Packages 80-pin LFQFP (PLQP0080KB-B) 12 × 12 mm, 0.5 mm pitch 64-pin LFQFP (PLQP0064KB-C) 10 × 10 mm, 0.5 mm pitch 64-pin LQFP (PLQP0064GA-A) 14 × 14 mm, 0.8 mm pitch 48-pin LFQFP (PLQP0048KB-B) 7 × 7 mm, 0.5 mm pitch 48-pin HWQFN (PWQN0048KC-A) 7 × 7 mm, 0.5 mm pitch 32-pin LQFP (PLQP0032GB-A) 7 × 7 mm, 0.8 mm pitch 32-pin HWQFN (PWQN0032KE-A) 5 × 5 mm, 0.5 mm pitch Debugging interfaces FINE interface Table 1.1 Outline of Specifications (4/4) Classification Module/Function Description |
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