R5F51406BDFK30 datasheet(3/118 Pages) RENESAS

3 / 118 page

R01DS0379EJ0110 Rev.1.10

Page 3 of 118

Apr 20, 2022

RX140 Group

1. Overview

Low power

consumption

Low power consumption

functions

• Module stop function

• Four low power consumption modes

Sleep mode, deep sleep mode, software standby mode, and snooze mode

Function for lower operating

power consumption

• Operating power control modes

High-speed operating mode, middle-speed operating mode, middle-speed operating mode 2 and low-

speed operating mode

Interrupt

Interrupt controller (ICUb)

• Interrupt vectors: 256

• External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)

• Non-maskable interrupts: 5 (The NMI pin, oscillation stop detection interrupt, voltage monitoring 1

interrupt, voltage monitoring 2 interrupt, and IWDT interrupt)

• 16 levels specifiable for the order of priority

DMA

Data transfer controller

(DTCb)

• Transfer modes: Normal transfer, repeat transfer, and block transfer

• Activation sources: Interrupts

• Sequence transfer

I/O ports

General I/O ports

80-pin/64-pin (ROM capacity: product with 128 Kbytes or more)/64-pins (ROM capacity: product with 64

Kbytes)/48-pin/32-pin

• I/O: 69/53/53/39/23

• Input: 3/3/1/1/1

• Pull-up resistors: 69/53/53/39/23

• Open-drain outputs: 47/35/35/27/20

• 5-V tolerance: 4/2/2/2/2

Event link controller (ELC)

• Event signals of 48 types can be directly connected to the module

• Operations of timer modules are selectable at event input

• Capable of event link operation for port B

Multi-function pin controller (MPC)

Capable of selecting the input/output function from multiple pins

Timers

Multi-function timer pulse

unit 2 (MTU2a)

• (16 bits × 6 channels) × 1 unit

• Up to 16 pulse-input/output lines and three pulse-input lines are available based on the six 16-bit

timer channels

• Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,

PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than

channel 5, for which only four signals are available.

• Input capture function

• 21 output compare/input capture registers

• Pulse output mode

• Complementary PWM output mode

• Reset synchronous PWM mode

• Phase-counting mode

• Capable of generating conversion start triggers for the A/D converter

Port output enable 2

(POE2a)

Controls the high-impedance state of the MTU’s waveform output pins

Compare match timer

(CMT)

• (16 bits × 2 channels) × 1 unit

• Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)

Independent watchdog

timer (IWDTa)

• 14 bits × 1 channel

• Count clock: Dedicated low-speed clock for the IWDT

Frequency divided by 1, 16, 32, 64, 128, or 256

Realtime clock (RTCB)

• Clock source: Sub-clock

• Calendar count mode or binary count mode selectable

• Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt

Low power timer (LPTa)

• 16 bits × 1 channel

• Clock source: Sub-clock, LOCO clock divided by 4, or dedicated low-speed clock for the IWDT

selectable

• Clock division ratio: Frequency divided by 1, 2, 4, 8, 16, or 32 selectable

• PWM output mode

8-bit timer (TMRa)

• (8 bits × 2 channels) × 2 units

• Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192)

and an external clock can be selected

• Pulse output and PWM output with any duty cycle are available

• Two channels can be cascaded and used as a 16-bit timer

Table 1.1

Outline of Specifications (2/4)

Classification

Module/Function

Description

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