R5F51406BDFK30 datasheet(76/118 Pages) RENESAS

tên linh kiện	R5F51406BDFK30

Giải thích chi tiết về linh kiện	48-MHz, 32-bit RX MCUs, on-chip FPU, 204 Coremark, up to 256-KB flash memory, up to 36 pins capacitive touch sensing unit, up to 9 comms channels, 12-bit A/D, D/A, RTC, IEC60730 compliance, 1.8-V to 5.5-V single supply, Encryption functions (optional)

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76 / 118 page

R01DS0379EJ0110 Rev.1.10

Page 76 of 118

Apr 20, 2022

RX140 Group

2. Electrical Characteristics

2.5.5.6

RIIC

Note:

tIICcyc: RIIC internal reference count clock (IICφ) cycle

Note 1. The value in parentheses is used when the ICMR3.NF[1:0] bits are set to 11b while a digital filter is enabled with the ICFER.NFE

bit = 1.

Note 2. Cb is the total capacitance of the bus lines.

Table 2.53

RIIC Timing

Conditions: 2.7 V

≤ VCC ≤ 5.5 V, 2.7 V ≤ AVCC0 ≤ 5.5 V, VSS = AVSS0 = 0 V, T

a = –40 to +105°C

Output load conditions: VOH = 0.7 × VCC, VOL = 0.3 × VCC, C = 30 pF

Item

Symbol

Min.*1

Max.

Unit

Test

Conditions

RIIC

(standard

mode, SMBus)

SCL cycle time

tSCL

6 (12) × tIICcyc + 1300

—

Figure 2.46

SCL high pulse width

tSCLH

3 (6) × tIICcyc + 300

—

SCL low pulse width

tSCLL

3 (6) × tIICcyc + 300

—

SCL, SDA rise time

tSr

—

1000

SCL, SDA fall time

tSf

—

300

SCL, SDA spike pulse removal time

tSP

01 (4) × tIICcyc

SDA bus free time

tBUF

3 (6) × tIICcyc + 300

—

START condition hold time

tSTAH

tIICcyc + 300

—

Repeated START condition setup time

tSTAS

1000

—

STOP condition setup time

tSTOS

1000

—

Data setup time

tSDAS

tIICcyc + 50

—

Data hold time

tSDAH

0—

SCL, SDA capacitive load

Cb*2

—

400

RIIC

(fast mode)

SCL cycle time

tSCL

6 (12) × tIICcyc + 600

—

Figure 2.46

SCL high pulse width

tSCLH

3 (6) × tIICcyc + 300

—

SCL low pulse width

tSCLL

3 (6) × tIICcyc + 300

—

SCL, SDA rise time

tSr

—

300

SCL, SDA fall time

tSf

—

300

SCL, SDA spike pulse removal time

tSP

01 (4) × tIICcyc

SDA bus free time

tBUF

3 (6) × tIICcyc + 300

—

START condition hold time

tSTAH

tIICcyc + 300

—

Repeated START condition setup time

tSTAS

300

—

STOP condition setup time

tSTOS

300

—

Data setup time

tSDAS

tIICcyc + 50

—

Data hold time

tSDAH

0—

SCL, SDA capacitive load

Cb*2

—

400

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