STLC4420A datasheet(37/40 Pages) STMICROELECTRONICS

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STLC4420A

Registers description

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5.14

DMA read length register

This 16 bit register is programmed with the maximum byte count of the next DMA Read

transfer. Only the low-order 16 bits are used. The value programmed can be any number of

bytes from 1 to 65535. A value of '0' disables the byte count logic, causing any transfers to

continue until terminated by clearing the Enable bit.

The format of the register is defined in Table 19.

5.15

DMA read base address register

The DMA read base address is written to point to the first location for the DMA Data register

read in the Devices AHB space. The address will be incremented after every Host access to

the Data register. There is no restriction on the Base Address. Byte, Half-word, Word and

QuadWord addresses are supported.

The format of the register is defined in Table 20.

Table 19.

DMA read length register

Bit number

Name

Description

31:16

Reserved

15:0

Data Length

Maximum byte count

Table 20.

DMA read length register

Bit number

Name

Description

31:0

DMA Read Base

Address for 1st DMA read

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