STLC4420A datasheet(27/40 Pages) STMICROELECTRONICS

27 / 40 page

STLC4420A

Serial host interface

27/40

4.6

Host multi-word writes

The Host may write to multiple consecutive 16-bit registers by keeping SPI_CSX asserted

and continuing to toggle SPI_CLK after the initial 16-bit data phase has completed.

The register address is incremented by 2 at the end of each data phase for all register

address except the DMA data register.

Consecutive writes to the DMA data register are written to the DMA data register with no

address increment.

4.7

Host reads

The Host reads from a 16-bit register by sending a 16 bit Address phase with A15 set to

one. The Address phase is followed by a 16-bit data phase. D15 is the first bit of data phase

and D0 is the last bit of the data phase. Data is available on SPI_DOUT.

Any register may be accessed during Sleep mode. However, the usual synchronization

mechanism for ARM or Shared clock domain registers is bypassed in Sleep mode. Read

data is unpredictable if the ARM writes to the ARM or Shared clock domain register during a

Sleep Mode read by the Host.

The SPI_CLK may stop at any time. The current phase (address or data) is not interrupted

by a stopped (or slowed) SPI_CLK. The logic remains in the current phase until SPI_CLK

resumes or SPI_CSX is de-asserted. If less than 16-bits are read by the host during a data

phase to any register except the DMA Data register there is no effect on the internal state of

the registers. If less than 16-bits are read by the host during a data phase to the DMA Data

Figure 18.

Serial host multi-word write

Figure 19.

Serial host multi-word write DMA data

STLC4420A bảng dữ liệu(PDF) 27 Page - STMicroelectronics