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WM8581 bảng dữ liệu(PDF) 25 Page - Wolfson Microelectronics plc

tên linh kiện WM8581
Giải thích chi tiết về linh kiện  Multichannel CODEC with S/PDIF Transceiver
PDF  94 Pages
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nhà sản xuất  WOLFSON [Wolfson Microelectronics plc]
Trang chủ  http://www.wolfsonmicro.com
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WM8581 bảng dữ liệu(HTML) 25 Page - Wolfson Microelectronics plc

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WM8581
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PP Rev 1.0 March 2006
25
Figure 15 Right Justified Mode Timing Diagram
I
2S MODE
In I
2S mode, the MSB of DIN1/2/3/4 is sampled on the second rising edge of BCLK following a
LRCLK transition. The MSB of the output data changes on the first falling edge of BCLK following an
LRCLK transition, and may be sampled on the next rising edge of BCLK. LRCLKs are low during the
left samples and high during the right samples.
Figure 16 I
2S Mode Timing Diagram
DSP MODE A
In DSP Mode A, the MSB of Channel 1 left data is sampled on the second rising edge of BCLK following a
LRCLK rising edge. Channel 1 right data then follows. For the PAIF Receiver, Channels 2 , 3 and 4 follow as
shown in Figure 17.
Figure 17 DSP Mode A Timing Diagram – PAIF Receiver Input Data



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