WM8581 datasheet(48/94 Pages) WOLFSON

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WM8581

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PP Rev 1.0 March 2006

Refer to Table 39 and Table 41 for details of the registers available for configuration in this mode.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PLLA 1/

DEVID1

00h

8:0

PLLA_K[8:0]

100100001

PLLA 2/

DEVID2

01h

7:0

PLLA_K[17:9]

101111101

3:0

PLLA_K[21:18]

1101

Fractional (K) part of PLLA

frequency ratio (R).

Value K is one 22-digit binary

number spread over registers R0,

R1 and R2 as shown.

PLLA 3/

DEVREV

02h

7:4

PLLA_N[3:0]

0111

Integer (N) part of PLLA frequency

ratio (R).

Use values in the range 5

PLLA_N

13 as close as possible to 8

PLLB 1

04h

8:0

PLLB_K[8:0]

100100001

PLLB 2

05h

8:0

PLLB_K[17:9]

101111110

3:0

PLLB_K[21:18]

1101

Fractional (K) part of PLLB

frequency ratio (R).

Value K is one 22-digit binary

number spread over registers R4,

R5 and R6 as shown.

Note: PLLB_K must be set to

specific values when the S/PDIF

receiver is used. Refer to S/PDIF

Receive Mode Clocking section

for details.

PLLB 3

06h

7:4

PLL_N[3:0]

0111

Integer (N) part of PLLB frequency

ratio (R).

Use values in the range 5

PLLB_N

13 as close as possible to 8

Note: PLLB_N must be set to

specific values when the S/PDIF

receiver is used. Refer to S/PDIF

Receive Mode Clocking section

for details.

Table 39 User Mode PLL_K and PLL_N Multiplier Control

Parameter

PLL User Mode

PLL S/PDIF Receiver Mode

PRESCALE_A

Manual

Write PRESCALE_B Value

PRESCALE_B

Manual

Configure Specified PLLB Frequency

PLLA_N

Manual

Automatically Controlled

PLLA_K

Manual

Automatically Controlled

PLLB_N

Manual

Configure Specified PLLB Frequency

PLLB_K

Manual

Configure Specified PLLB Frequency

FREQMODE_A

Manual

Automatically Controlled

FREQMODE_B

Manual

Not Used

POSTSCALE_A

Manual

256fs/128fs PLLACLK Select

POSTSCALE_B

Manual

Not Used

Table 40 PLL Control Register Function in PLL User and PLL S/PDIF Receiver Modes

PLL CONFIGURATION

The PLLs perform a configurable frequency multiplication of the input clock signal (f1). The multiplication

factor of the PLL (denoted by ‘R’) is variable and is defined by the relationship: R = (f2 ÷ f1).

The multiplication factor for each PLL is set using register bits PLLx_N and PLLx_K (refer to Table 39). The

multiplication effect of both the N and K multipliers are additive (i.e. if N is configured to provide a

multiplication factor of 8 and K is configured to provide a multiplication factor of 0.192, the overall

multiplication factor is 8 + 0.192 = 8.192).

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