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WM8581 bảng dữ liệu(PDF) 45 Page - Wolfson Microelectronics plc

tên linh kiện WM8581
Giải thích chi tiết về linh kiện  Multichannel CODEC with S/PDIF Transceiver
PDF  94 Pages
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WM8581 bảng dữ liệu(HTML) 45 Page - Wolfson Microelectronics plc

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WM8581
w
PP Rev 1.0 March 2006
45
SECONDARY AUDIO INTERFACES (SAIF RX & SAIF TX)
The Transmit and Receive sides of the Secondary Audio Interface share a common LRCLK and a
common BCLK. These can be supplied externally (slave mode) or they can be generated internally
by the WM8581 (master mode). The master mode LRCLK/BCLK are created by the Master Mode
Clock Gen module. The control of this module is described on page 34. The clock supplied to this
module can be ADCMCLK, PLLACLK, PLLBCLK, or MCLK and is selected using the
SAIFMS_CLKSEL register. If the digital routing has been configured such that the SAIF Transmitter
is sourcing the S/PDIF Receiver, then PLLACLK is automatically selected, and it is recommended
that the interface operate in master mode. However, if the SAIF Transmitter sources something other
than the S/PDIF Receiver, and the S/PDIF Receiver is powered up, the PLLACLK and PLLBCLK are
invalid for SAIF operation, so the choice is limited to ADCMCLK (default) or MCLK.
Figure 30 SAIF Clock Selection
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R11
7:6
SAIFMS_
CLKSEL
11
SAIF Master Mode clock source
00 = ADCMCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
Table 36 SAIF Master Mode Clock Control



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