WM8581 datasheet(40/94 Pages) WOLFSON

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WM8581

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PP Rev 1.0 March 2006

CLOCK SELECTION

To accompany the flexible digital routing options, the WM8581 offers a clock configuration scheme

for each interface. The user can choose the interface clock from MCLK, ADCMCLK, PLLACLK or

PLLBCLK. For some interfaces, the rate can be controlled either by external LRCLK (slave mode),

internal LRCLK (master mode) or by control register. The available options are described below.

DAC INTERFACE

The DAC_CLKSEL register selects the DAC clock source from MCLK, PLLACLK or PLLBCLK. If the

digital routing has been set such that the DAC1 is sourcing the S/PDIF Receiver, then PLLACLK is

automatically selected, and DACs 2/3/4 are powered down. The rate that the DACs operate at is

determined by the DAC Rate module. It calculates the rate based on the digital routing setup. When

sourcing from the PAIF Receiver, PAIFRX_LRCLK (internal or external) is used in the rate

calculation. . When sourcing from the SAIF Receiver, SAIF_LRCLK (internal or external) is used in

the rate calculation. The SFRM_CLK is used in the rate calculation when the DAC1 sources from the

S/PDIF Receiver, however this can be changed by setting the RX2DAC_MODE register bit. With

RX2DAC_MODE set, the PAIFRX_LRCLK determines the rate, and DACs 2/3/4 source the PAIF

Receiver (and are no longer automatically powered down).

Figure 25 DAC Clock Selection

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

1:0

DAC_CLKSEL

DAC clock source

00 = MCLK pin

01 = PLLACLK

10 = PLLBCLK

11 = MCLK pin

R15

RX2DAC_MODE

DAC Rate and Power down control

(only valid when DAC_SRC = 00)

0 = SFRM_CLK determines rate,

DACs 2/3/4 powered down

1 = PAIFRX_LRCLK determines

rate, DACs 2/3/4 source PAIFRX

Table 32 DAC Clock Control

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