STM32G041C6 datasheet(23/121 Pages) STMICROELECTRONICS

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DS12993 Rev 3

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STM32G041x6/x8

Functional overview

3.13.1

Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It

handles physical line events associated with a non-maskable interrupt (NMI) and maskable

interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.

The tight coupling of the processor core with NVIC significantly reduces the latency between

interrupt events and start of corresponding interrupt service routines (ISRs). The ISR

vectors are listed in a vector table, stored in the NVIC at a base address. The vector

address of an ISR to execute is hardware-built from the vector table base address and the

ISR order number used as offset.

If a higher-priority interrupt event happens while a lower-priority interrupt event occurring

just before is waiting for being served, the later-arriving higher-priority interrupt event is

served first. Another optimization is called tail-chaining. Upon a return from a higher-priority

ISR then start of a pending lower-priority ISR, the unnecessary processor context

unstacking and stacking is skipped. This reduces latency and contributes to power

efficiency.

Features of the NVIC:

•

Low-latency interrupt processing

•

4 priority levels

•

Handling of a non-maskable interrupt (NMI)

•

Handling of 32 maskable interrupt lines

•

Handling of 10 Cortex-M0+ exceptions

•

Later-arriving higher-priority interrupt processed first

•

Tail-chaining

•

Interrupt vector retrieval by hardware

3.13.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and

allows identifying wake-up events at processor wakeup from Stop mode.

The EXTI controller has a number of channels, of which some with rising, falling or rising,

and falling edge detector capability. Any GPIO and a few peripheral signals can be

connected to these channels.

The channels can be independently masked.

The EXTI controller can capture pulses shorter than the internal clock period.

A register in the EXTI controller latches every event even in Stop mode, which allows the

software to identify the origin of the processor's wake-up from Stop mode or, to identify the

GPIO and the edge event having caused an interrupt.

3.14

Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32G041x6/x8 devices. It

can be extended to 16-bit resolution through hardware oversampling. The ADC has up to 16

external channels and 3 internal channels (temperature sensor, voltage reference, VBAT

monitoring). It performs conversions in single-shot or scan mode. In scan mode, automatic

conversion is performed on a selected group of analog inputs.

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