STM32G041C6 datasheet(21/121 Pages) STMICROELECTRONICS

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DS12993 Rev 3

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STM32G041x6/x8

Functional overview

•

System clock source: three different sources can deliver SYSCLK system clock:

–

4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It

can supply clock to system PLL. The HSE can also be configured in bypass mode

for an external clock.

–

16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can

supply clock to system PLL.

–

System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or

HSI16 clocks.

•

Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

–

32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an

external clock.

–

32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

•

Peripheral clock sources: several peripherals (RNG, I2S, USARTs, I2Cs, LPTIMs,

ADC) have their own clock independent of the system clock.

•

Clock security system (CSS): in the event of HSE clock failure, the system clock is

automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE

clock failure can also be detected and generate an interrupt. The CCS feature can be

enabled by software.

•

Clock output:

–

MCO (microcontroller clock output) provides one of the internal clocks for

external use by the application

–

LSCO (low speed clock output) provides LSI or LSE in all low-power modes

(except in VBAT operation).

Several prescalers allow the application to configure AHB and APB domain clock

frequencies, 64 MHz at maximum.

3.10

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of

the GPIO pins are shared with special digital or analog functions.

Through a specific sequence, this special function configuration of I/Os can be locked, such

as to avoid spurious writing to I/O control registers.

3.11

Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with

single-AHB architecture.

With 5 channels, it performs data transfers between memory-mapped peripherals and/or

memories, to offload the CPU.

Each channel is dedicated to managing memory access requests from one or more

peripherals. The unit includes an arbiter for handling the priority between DMA requests.

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