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STM32WB50CG bảng dữ liệu(PDF) 109 Page - STMicroelectronics

tên linh kiện STM32WB50CG
Giải thích chi tiết về linh kiện  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 or 802.15.4 radio solution
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STM32WB50CG bảng dữ liệu(HTML) 109 Page - STMicroelectronics

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DS13047 Rev 5
109/119
STM32WB50CG STM32WB30CE
Electrical characteristics
110
Figure 26. SPI timing diagram - master mode
1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.
JTAG/SWD interface characteristics
Unless otherwise specified, the parameters given in Table 83 and Table 84 are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 20: General operating conditions. with the following
configuration:
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5 ₓ VDD
ai14136c
CPHA= 0
MOSI
OUTPUT
MISO
INP UT
CPHA= 0
LSB OUT
LSB IN
CPOL=0
CPOL=1
B I T1 OUT
NSS input
tc(SCK)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
th(MI)
High
CPHA=1
CPHA=1
CPOL=0
CPOL=1
tsu(MI)
tv(MO)
th(MO)
MSB IN
BIT6 IN
MSB OUT
Table 83. JTAG characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1/tc(TCK)
TCK clock frequency
2.7 < VDD < 3.6 V
-
-
29
MHz
2.0 < VDD < 3.6 V
-
-
21
tisu(TMS)
TMS input setup time
-
2.5
-
-
ns
tih(TMS)
TMS input hold time
-
2
-
-
tisu(TDI)
TDI input setup time
-
1.5
-
-
tih(TDI)
TDI input hold time
-
2
-
-
tov(TDO)
TDO output valid time
2.7 < VDD < 3.6 V
-
13.5
16.5
2.0 < VDD < 3.6 V
-
13.5
23
toh(TDO)
TDO output hold time
-
11
-
-



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