STM32WB50CG datasheet(29/119 Pages) STMICROELECTRONICS

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DS13047 Rev 5

29/119

STM32WB50CG STM32WB30CE

Functional overview

IPCC

HSEM

PKA

GPIOs

(13)

pins

(14)

pins

1. Legend: Y = Yes (enabled), O = Optional (disabled by default, can be enabled by software), R = Data retained,



- = Not available.

2. Standby with SRAM2a Retention mode only.

3. Flash memory programming only possible in Run, not in Low Power Run.

4. The Flash memory can be configured in Power-down mode. By default, it is not in Power-down Run.

5. The SRAM clock can be gated on or off.

6. SRAM2a content is preserved when the bit RRS is set in PWR_CR3 register.

7. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by

the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not

need it anymore.

8. The HSE can be used by the RF subsystem according with the need to perform RF operation (Tx or Rx).

9. MSI maximum frequency.

10. In case RF will be used and HSE will fail.

11. UART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame

event.

12. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.

13. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.

14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when

exiting the Shutdown mode.

Table 5. Features over all modes(1) (continued)

Peripheral

Stop0/Stop1

Stop 2

Standby

Shutdown

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