STM32WB50CG datasheet(75/119 Pages) STMICROELECTRONICS

tên linh kiện	STM32WB50CG

Giải thích chi tiết về linh kiện	Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 or 802.15.4 radio solution

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75 / 119 page

DS13047 Rev 5

75/119

STM32WB50CG STM32WB30CE

Electrical characteristics

110

6.3.9

Wakeup time from Low-power modes and voltage scaling



transition times

The wakeup times given in Table 45 are the latency between the event and the execution of

the first user instruction.

The device goes in Low-power mode after the WFE (Wait For Event) instruction.

APB1

RTC

1.10

1.25

µA/MHz

I2C1 independent clock domain

2.50

4.40

I2C1 clock domain

4.80

5.50

LPTIM1 independent clock domain

2.10

3.00

LPTIM1 clock domain

3.60

3.80

TIM2

5.65

4.90

LPTIM2 clock domain

3.95

4.50

LPTIM2 independent clock domain

2.20

3.80

WWDG

0.335

0.965

All APB1 peripherals

17.0

13.55

APB2

AHB to APB2(3)

1.10

1.35

TIM1

8.20

7.25

TIM17

2.85

2.40

TIM16

2.75

2.55

USART1 independent clock domain

4.40

7.00

USART1 clock domain

8.80

7.75

SPI1

1.75

1.45

All APB2 on

25.5

ALL

72.2

62.9

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. GPIOs consumption during read and write accesses.

3. The AHB to APB2 bridge is automatically active when at least one peripheral is ON on the APB2.

Table 44. Peripheral current consumption (continued)

Peripheral

Run

Low-power

run and sleep

Unit

Table 45. Low-power mode wakeup timings(1)

Symbol

Parameter

Conditions

Typ

Max

Unit

tWUSLEEP

Wakeup time from

Sleep mode



to Run mode

-9

No. of

CPU

cycles

tWULPSLEEP

Wakeup time from



Low-power sleep mode

to Low-power run mode

Wakeup in Flash with memory in power-down

during low-power sleep mode (FPDS = 1 in

PWR_CR1) and with clock MSI = 2 MHz

910

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