SPC58NH84C3 datasheet(62/147 Pages) STMICROELECTRONICS

62 / 147 page

Electrical characteristics

SPC58EHx, SPC58NHx

62/147

DS12304 Rev 5

ΔTUE10

TUE degradation due

to VDD_HV_ADR offset

with respect to

VDD_HV_ADV

VIN < VDD_HV_ADV

VDD_HV_ADR − VDD_HV_ADV ∈

[0:25 mV]

–1.0

1.0

LSB

(10b)

VIN < VDD_HV_ADV

VDD_HV_ADR − VDD_HV_ADV ∈

[25:50 mV]

–2.0

2.0

VIN < VDD_HV_ADV

VDD_HV_ADR − VDD_HV_ADV ∈

[50:75 mV]

–3.5

3.5

VIN < VDD_HV_ADV

VDD_HV_ADR − VDD_HV_ADV ∈

[75:100 mV]

–6.0

6.0

VDD_HV_ADV < VIN <

VDD_HV_ADR

VDD_HV_ADR − VDD_HV_ADV ∈

[0:25 mV]

–2.5

2.5

VDD_HV_ADV < VIN <

VDD_HV_ADR

VDD_HV_ADR − VDD_HV_ADV ∈

[25:50 mV]

–4.0

4.0

VDD_HV_ADV < VIN <

VDD_HV_ADR

VDD_HV_ADR − VDD_HV_ADV ∈

[50:75 mV]

–7.0

7.0

VDD_HV_ADV < VIN <

VDD_HV_ADR

VDD_HV_ADR − VDD_HV_ADV ∈

[75:100 mV]

–12.0

12.0

TUEINJ2

TUE degradation

addition, due to current

injection in IINJ2

range.(5)

See Operating Conditions

chapter Table 5, IINJ2

parameter.

3LSB

DNL(7)

Differential non-linearity

std. mode

Standard frequency mode,

VDD_HV_ADV > 4 V

VDD_HV_ADR_S > 4 V

–1

LSB

(10b)

High frequency mode,

VDD_HV_ADV > 4 V

VDD_HV_ADR_S > 4 V

–1

1. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal

sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within

the sampling window. Refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing

and calculating the sampling window duration.

2. In case the ADC is used as Fast Comparator the sampling time is tADCSAMPLE = 2/fADCK.

3. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven

by the transfer of charge between internal capacitances during the conversion.

Table 28. ADC-Comparator electrical specification (continued)

Symbol

Parameter

Conditions

Value

Unit

Min

Max

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