công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

Preview PDF HTML

SPC58NH84C3 bảng dữ liệu(PDF) 48 Page - STMicroelectronics

tên linh kiện SPC58NH84C3
Giải thích chi tiết về linh kiện  SPC58 H Line - 32 bit Power Architecture automotive MCU Triple z4 cores 200 MHz, 10 MBytes Flash, HSM, ASIL-D
PDF  147 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

SPC58NH84C3 bảng dữ liệu(HTML) 48 Page - STMicroelectronics

Back Button SPC58NH84C3 Datasheet HTML 44Page - STMicroelectronics SPC58NH84C3 Datasheet HTML 45Page - STMicroelectronics SPC58NH84C3 Datasheet HTML 46Page - STMicroelectronics SPC58NH84C3 Datasheet HTML 47Page - STMicroelectronics SPC58NH84C3 Datasheet HTML 48Page - STMicroelectronics SPC58NH84C3 Datasheet HTML 49Page - STMicroelectronics SPC58NH84C3 Datasheet HTML 50Page - STMicroelectronics SPC58NH84C3 Datasheet HTML 51Page - STMicroelectronics SPC58NH84C3 Datasheet HTML 52Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 48 / 147 page
background image
Electrical characteristics
SPC58EHx, SPC58NHx
48/147
DS12304 Rev 5
|ΔPLL0PHI1SPJ|(3) CC
D
PLL0_PHI1 single period
jitter
fPLL0IN = 20 MHz
(resonator)
fPLL0PHI1 = 40 MHz,
6-sigma pk-pk
—
—
300(4)
ps
ΔPLL0LTJ(3)
CC
D
PLL0 output long term
jitter(4)
fPLL0IN = 20 MHz
(resonator), VCO
frequency = 800 MHz
10 periods
accumulated jitter
(80 MHz equivalent
frequency), 6-sigma
pk-pk
—
—
±250
ps
16 periods
accumulated jitter
(50 MHz equivalent
frequency), 6-sigma
pk-pk
—
—
±300
ps
long term jitter
(< 1 MHz equivalent
frequency), 6-sigma
pk-pk)
—
—
±500
ps
IPLL0
CC
D PLL0 consumption
FINE LOCK state
—
—
6
mA
1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted
when using internal RCOSC or external oscillator is used in functional mode.
2. If the PLL0_PHI1 is used as an input for PLL1, then the PLL0_PHI1 frequency shall obey the maximum input frequency
limit set for PLL1 (87.5 MHz, according to Table 21).
3. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to
the output CLKOUT pin.
4. VDD_LV noise due to application in the range VDD_LV = 1.20 V±5%, with frequency below PLL bandwidth (40 kHz) will be
filtered.
Table 20. PLL0 electrical characteristics (continued)
Symbol
C
Parameter
Conditions
Value
Unit
Min
Typ
Max



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com