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STM32WB35CC bảng dữ liệu(PDF) 188 Page - STMicroelectronics |
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STM32WB35CC bảng dữ liệu(HTML) 188 Page - STMicroelectronics |
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188 / 193 page ![]() Revision history STM32WB55xx STM32WB35xx 188/193 DS11929 Rev 11 08-Oct-2018 3 Changed document classification to Public. Updated Features, Section 3.6.2: BLE general description, Section 3.7.2: Power supply schemes, Section 3.7.3: Linear voltage regulator, Section 3.10: Clocks and startup, Section 6.3.10: External clock source characteristics, Section 6.3.20: Analog-to-Digital converter characteristics, Section 6.3.29: Communication interfaces characteristics, Section 7.2: WLCSP100 package information and Section 7.5: Thermal characteristics. Replaced VDDIOx with VDD throughout the whole document. Updated Table 5: Typical external components, footnote 2 of Table 7: Features over all modes, Table 8: STM32WB55xx modes overview and its footnote 5, Table 12: Internal voltage reference calibration values, Table 16: STM32WB55xx pin and ball definitions and its footnote 6, Table 17: Alternate functions, Table 20: Thermal characteristics, Table 21: Main performance at VDD = 3.3 V, Table 21: Main performance at VDD = 3.3 V, Table 22: General operating conditions, Table 23: RF transmitter BLE characteristics and its footnote, Table 26: RF receiver BLE characteristics (1 Mbps), Table 28: RF BLE power consumption for VDD = 3.3 V, Table 29: RF transmitter 802.15.4 characteristics and its footnote 1, Table 30: RF receiver 802.15.4 characteristics, Table 31: RF 802.15.4 power consumption for VDD = 3.3 V, Table 34: Embedded internal voltage reference, Table 35: Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V, Table 36: Current consumption in Run and Low-power run modes, code with data processing running from SRAM1, VDD = 3.3 V, Table 37: Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V, Table 38: Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1, VDD = 3.3 V, Table 39: Current consumption in Sleep and Low-power sleep modes, Flash memory ON, Table 40: Current consumption in Low-power sleep modes, Flash memory in Power down, Table 41: Current consumption in Stop 2 mode, Table 42: Current consumption in Stop 1 mode, Table 43: Current consumption in Stop 0 mode, Table 44: Current consumption in Standby mode, Table 45: Current consumption in Shutdown mode, Table 46: Current consumption in VBAT mode, Table 47: Current under Reset condition, Table 48: Peripheral current consumption, Table 49: Low- power mode wakeup timings, Table 50: Regulator modes transition times, Table 51: Wakeup time using LPUART, Table 53: HSE clock source requirements and added footnote to it, Table 61: LSI2 oscillator characteristics, Table 63: Flash memory characteristics, Table 65: EMS characteristics, Table 67: ESD absolute maximum ratings, Table 69: I/O current injection susceptibility, Table 70: I/O static characteristics and its footnotes, Table 71: Output voltage characteristics, Table 72: I/O AC characteristics and its footnotes 1 and 2, Table 73: NRST pin characteristics, Table 77: ADC accuracy - Limited test conditions 1, Table 78: ADC accuracy - Limited test conditions 2, Table 79: ADC accuracy - Limited test conditions 3, Table 80: ADC accuracy - Limited test conditions 4, Table 82: COMP characteristics, Table 90: I2C analog filter characteristics, Table 91: SPI characteristics, Table 92: Quad-SPI characteristics in SDR mode, Table 93: Quad-SPI characteristics in DDR mode and Table 94: SAI characteristics. Table 107. Document revision history (continued) Date Revision Changes |
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