PC8374L datasheet(114/239 Pages) NSC

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6.0 General-Purpose Input/Output (GPIO) Ports (Continued)

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Revision1.1

6.3.2

System Notification

System notification on GPIO-triggered events is achieved by asserting at least one of the following output pins:

• Interrupt Request (via the Interrupt Serializer in the LPC Bus Interface).

• System Management Interrupt (SMI).

The system notification for each GPIO pin is controlled by the corresponding bit in GPEVEN register together with the bits

of GPEVR register. System notification by a GPIO pin is enabled if the corresponding bit of GPEVEN register is set to 1. The

bits of the GPEVR register select the means of system notification (IRQ, SMI) that the detected GPIO event is routed to. The

event routing mechanism is shown in Figure 18.

Figure 18. GPIO Event Routing Mechanism for System Notiﬁcation

The system notification to the target is asserted if at least one GPIO pin is in event pending state.

The selection of the target (for system notification) is determined by the GPEVR register. The specific IRQ number is deter-

mined by the IRQ selection procedure of the device configuration. The assertion of IRQ (as a means of system notification)

is disabled either when the GPIO functional block is deactivated or when VDD3 power is off.

The assertion of SMI is independent of the activation of the GPIO functional block.

System notification through IRQ, SMI or SCI (see Section 4.2.4 on page 86) can be initiated by software by writing to the

Data Out bit (in GPDO or GPDIO register) of a GPIO pin. This is possible only if the output of the corresponding GPIO pin

is enabled, pin multiplexing is selected for the GPIO function (see Section 1.3 on page 16) and the GPIO event is routed to

IRQ, SMI or SCI. System notification is asserted according to the actual level at the GPIO pin driven by the GPIO output

and/or by external circuitry. The level driven by the GPIO output should not cause a contention with the level driven by the

external circuitry.

A pending edge event may be cleared by clearing the corresponding GPEVST bit. However, a level event source may not

be released by software (except for disabling the source) as long as the pin is at active level. When level event is used, it is

also recommended to disable the input debouncer.

On deactivation of the GPIO functional block and while VDD3 power is off, access through the LPC bus to the runtime regis-

ters (GPEVST and GPEVEN) is disabled. All means of system notification that include the target IRQ number are detached

from the GPIO and de-asserted.

When VDD3 power is off, the status bits of the VDD-powered GPIO pins (VDDLOAD = 1) are cleared, however the status bits

of the VSB-powered GPIO pins (VDDLOAD = 0) are not affected.

Before enabling any system notification, it is recommended to set the desired event configuration and then verify that the

status registers are cleared.

Event Pending Indicator

IRQ

Event

Routing

Logic

Enable

IRQ

GPIO Pin Event Routing Register

Bit 0

Routed Events

from other GPIO Pins

Routing

SMI

Bit 1

Routing

Enable

SMI

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