PC8374L datasheet(47/239 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.1

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The memory mapping of Logical Devices control and configuration registers (I/O indexes 30h-FFh) are enabled by MEM-

MAP register (see Section 3.7.1 on page 52). When enabled for memory access, these registers are grouped to 32 byte

banks, one for each Logical Device as shown on Figure 8. Table 21 provides the conversion between I/O offsets and mem-

ory offsets of these registers for Logical Device number N. The offsets specified in the table should be added to

MEM_BASE+7C00h+N*20h to get the memory physical address

Table 21. Memory Physical Addresses of Logical Device Conﬁguration Registers

I/O Index

Memory Offset

Logical Device Control (Activate)

30h

00h

Memory Base Descriptor

50h

01h

I/O Base Address Descriptor 0 Bits 15-8

60h

03h

I/O Base Address Descriptor 0 Bits 7-0

61h

04h

I/O Base Address Descriptor 1 Bits 15-8

62h

05h

I/O Base Address Descriptor 1 Bits 7-0

63h

06h

I/O Base Address Descriptor 2 Bits 15-8

64h

07h

I/O Base Address Descriptor 2 Bits 7-0

65h

08h

I/O Base Address Descriptor 3 Bits 15-8

66h

09h

I/O Base Address Descriptor 3 Bits 7-0

67h

0Ah

Interrupt Number and Wake-Up on IRQ Enable

70h

0Bh

IRQ Type Select

71h

0Ch

DMA Channel Select 0

74h

0Dh

DMA Channel Select 1

75h

0Eh

Device Speciﬁc Logical Device Conﬁguration

F0h - FFh

10h to 1Fh

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