PC8374L datasheet(49/239 Pages) NSC

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3.0 Device Architecture and Configuration (Continued)

Revision 1.1

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3.4 INTERNAL ADDRESS DECODING

A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional

blocks. However, the number of configurable bits in the base address registers varies for each logical device.

The lower 1, 2, 3, 4 or 5 address bits are decoded in the functional block to determine the offset of the accessed register

within the logical device’s I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the base

address register to decode the entire I/O range allocated to the logical device. Therefore, the lower bits of the base address

register are forced to 0 (read-only), and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size

of the I/O range.

The base address of the FDC, Serial Port 1, Serial Port 2, InfraRed Port, and KBC are limited to the I/O address range of

00h to 7FXh only (bits 15-11 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to

3F8h. The addresses of all of the non-legacy logical devices, including the Health Management, SWC and GPIO, are con-

figurable within the full 16-bit address range (up to FFFXh).

In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the Parallel

Port). The KBC has two I/O base addresses with some implied dependency between them. For more details, see the de-

scription of the base address register for each logical device.

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