© VITESSE SEMICONDUCTOR CORPORATION

Page 3

11/9/99

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC8166

2.488 Gbit/sec

1:16 SONET/SDH Demux with Clock Recovery

G52252-0, Rev. 3.0

Low Speed Interface

The demultiplexed serial stream is made available by a 16 bit differential LVPECL interface D(15:0)+ with

speed LVPECL output drivers are designed to drive a 50

Ω transmission line. The transmission line can be DC

terminated with a split end termination scheme, see Figure 2, or DC terminated by 50

Ω to V

see Figure 3. At any time, the equivalent split-end termination technique can be substituted for the traditional

50

Ω to V

coupling method for the occasion when the downstream device provides the bias point for AC coupling. If the

downstream device were to have internal termination, the line to line 100

Ω resistor may not be necessary. The

divide by 32 output can be used to provide a reference clock for the clock multiplication unit on the VSC8163.

Figure 2: Split-end DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs

Figure 3: Traditional DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs

VSC8166

R2

R2

R1

R1

VEE

VCC

downstream

R1 = 125

Ω R2 = 83Ω, Zo=50Ω, V

R1+R2

R1 =50

Ω

VSC8166

R1 =50

Ω

downstream