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AD4116BCPZ bảng dữ liệu(PDF) 6 Page - Analog Devices

tên linh kiện AD4116BCPZ
Giải thích chi tiết về linh kiện  Single Supply, 24-Bit, Sigma-Delta ADC with 짹10 V, 10 M廓 Inputs and Buffered Low Level Inputs
PDF  59 Pages
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nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
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AD4116
Data Sheet
Rev. 0 | Page 6 of 59
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Crystal
Frequency
14
16
16.384
MHz
Start-Up Time
10
µs
External Clock (CLKIO)
4
4.096
MHz
Duty Cycle
30
50
70
%
LOGIC INPUTS
Input Voltage4
High, VINH
2 V ≤ IOVDD < 2.3 V
0.65 × IOVDD
V
2.3 V ≤ IOVDD ≤ 5.5 V
0.7 × IOVDD
V
Low, VINL
2 V ≤ IOVDD < 2.3 V
0.35 × IOVDD
V
2.3 V ≤ IOVDD ≤ 5.5 V
0.7
V
Hysteresis
IOVDD ≥ 2.7 V
0.08
0.25
V
IOVDD < 2.7 V
0.04
0.2
V
Leakage Current
−10
+10
µA
LOGIC OUTPUT (DOUT/RDY)
Output Voltage4
High, VOH
IOVDD ≥ 4.5 V, ISOURCE = 1 mA
0.8 × IOVDD
V
2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 µA
0.8 × IOVDD
V
IOVDD < 2.7 V, ISOURCE = 200 µA
0.8 × IOVDD
V
Low, VOL
IOVDD ≥ 4.5 V, ISINK = 2 mA
0.4
V
2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA
0.4
V
IOVDD < 2.7 V, ISINK = 400 µA
0.4
V
Leakage Current4
Floating state
−10
+10
µA
Output Capacitance
Floating state
10
pF
POWER REQUIREMENTS
Power Supply Voltage
AVDD to AVSS
4.5
5.5
V
AVSS to DGND
−2.75
0
V
IOVDD to DGND
2
5.5
V
IOVDD to AVSS
For AVSS < DGND
6.35
V
POWER SUPPLY CURRENTS7
All outputs unloaded, digital inputs
connected to IOVDD or DGND
Full Operating Mode
AVDD Current
Including internal reference
5.3
6.63
mA
IOVDD Current
Internal clock
0.85
1.12
mA
Standby Mode
All VIN = 0 V
45
µA
Power-Down Mode
All VIN = 0 V
20
µA
POWER DISSIPATION
Full Operating Mode
31
mW
Standby Mode
223
µW
Power-Down Mode
100
µW
1
The full specification is guaranteed for a differential input signal of ±10 V. The device is functional up to a differential input signal of ±VREF × 10. However, the specified
absolute (pin) voltage must not be exceeded for proper function.
2
Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. An internal zero-scale calibration
at low level inputs reduces the offset error in the order of the noise for the programmed output data rate selected.
3
To improve performance, use an external reference with better accuracy and lower temperature coefficient.
4
Specification is not production tested but is supported by characterization data at the initial product release.
5
Following a system full-scale calibration, the gain error is reduced to the order of the noise for the programmed output data rate.
6
This specification includes moisture sensitivity level (MSL) preconditioning effects.
7
This specification is with no load on the REFOUT pin and the digital output pins.



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