AD4116BCPZ datasheet(44/59 Pages) AD

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AD4116

Data Sheet

Rev. 0 | Page 44 of 59

Alternate Synchronization

In alternate synchronization mode, the SYNC input operates as

a start conversion command when several channels of the

AD4116 are enabled. Setting the ALT_SYNC bit in the interface

mode register to 1 enables an alternate synchronization scheme.

When the SYNC input is taken low, the ADC completes the

conversion on the enabled channel, selects the next channel in

the sequence, and then waits until the SYNC input is taken high

to start the conversion. The RDY output goes low when the

conversion is complete on the current channel, and the data

the SYNC input does not interfere with the sampling on the

currently selected channel but allows the user to control the

instant at which the conversion begins on the next channel in

the sequence.

Alternate synchronization mode can be used only when several

channels are enabled. It is not recommended to use this mode

when a single channel is enabled.

ERROR FLAGS

The status register contains three error bits (ADC_ERROR,

CRC_ERROR, and REG_ERROR) that flag errors with the

ADC conversion, errors with the CRC check, and errors caused

by changes in the registers, respectively. In addition, the

ERROR output can indicate that an error has occurred.

ADC_ERROR

The ADC_ERROR bit in the status register flags any errors that

occur during the conversion process. The flag is set when an

overrange or underrange result is output from the ADC. The

ADC also outputs all 0s or all 1s when an undervoltage or

overvoltage occurs. This flag is reset only when the overvoltage or

undervoltage is removed. This flag is not reset by a read of the

data register.

CRC_ERROR

If the CRC value that accompanies a write operation does not

correspond with the information sent, the CRC_ERROR flag is

set. The flag is reset as soon as the status register is explicitly read.

REG_ERROR

The REG_ERROR flag is used in conjunction with the

REG_CHECK bit in the interface mode register. When the

REG_CHECK bit is set, the AD4116 monitors the values in

the on-chip registers. If a bit changes, the REG_ERROR bit is

set to 1. Therefore, for writes to the on-chip registers, set the

REG_CHECK bit to 0. When the registers are updated, the

REG_CHECK bit can be set to 1. The AD4116 calculates a

checksum of the on-chip registers. If one of the register values

has changed, the REG_ERROR bit is set to 1. If an error is

flagged, the REG_CHECK bit must be set to 0 to clear the

REG_ERROR bit in the status register. The register check

function does not monitor the data register, status register, or

interface mode register.

ERROR Input/Output

The ERROR pin functions as an error input and output pin or

as a general-purpose output pin. The ERR_EN bits in the

GPIOCON register determine the function of the pin.

When the ERR_EN bits are set to 10, the ERROR pin functions

as an open-drain error output. The three error bits in the status

OR’ed, inverted, and mapped to the ERROR output. Therefore,

the ERROR output indicates that an error has occurred. The

status register must be read to identify the error source.

When the ERR_EN bits are set to 01, The ERROR pin functions

as an error input. The error output of another component can

be connected to the AD4116 ERROR input so that the AD4116

indicates when an error occurs on either itself or the external

component. The value on the ERROR input is inverted and

OR’ed with the errors from the ADC conversion, and the result

is indicated via the ADC_ERROR bit in the status register. The

value of the ERROR input is reflected in the ERR_DAT bit in

the GPIOCON register.

The ERROR input and output is disabled when the ERR_EN

bits are set to 00. When the ERR_EN bits are set to 11, the

ERROR pin operates as a general-purpose output where the

ERR_DAT bit is used to determine the logic level of the pin.

DATA_STAT

The contents of the status register can be appended to each

conversion on the AD4116 using the DATA_STAT bit in the

IFMODE register. This function is useful if several channels are

enabled. Each time a conversion is output, the contents of the

status register are appended. The four LSBs of the status register

indicate to which channel the conversion corresponds. In

addition, the user can determine if any errors are being flagged

by the error bits.

IOSTRENGTH

The SPI can operate with a power supply as low as 2 V.

However, at this low voltage, the DOUT/RDY pin may not

have sufficient drive strength if there is moderate parasitic

capacitance on the board or if the SCLK frequency is high. The

IOSTRENGTH bit in the interface mode register increases the

drive strength of the DOUT/RDY pin.

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