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W5300 bảng dữ liệu(PDF) 16 Page - WIZnet Co., Ltd

tên linh kiện W5300
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W5300 bảng dữ liệu(HTML) 16 Page - WIZnet Co., Ltd

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16
Host selects W5300 at the W5300 read/write operation.
When /CS is de-asserted high, DATA[15:0] are driven as High-Z.
/WR
IL
WRITE ENABLE
Write enable signal.
Host writes W5300 register addressed by ADDR[9:0] to DATA[15:0].
DATA[15:0] are latched in the W5300 register according to the
configuration of the Write-data-fetch-timing.
Refer to 13-11th bit(WDF[2:0] of MR).
/RD
IL
READ ENABLE
Read enable signal.
Host
reads
W5300
register
addressed
by
ADDR[9:0]
through
DATA[15:0].
/INT
OL
INTERRUPT
Interrupt Request Signal.
It is asserted low when interrupt(connected, disconnected, data
received, data sent or timeout) occurs on operating.
When interrupt service is completed by host and Interrupt register(IR) is
cleared by host, it is de-asserted high.
Refer
to
IR,
Interrupt
Mask
Register(IMR),
SOCKETn
Interrupt
Register(Sn_IR), SOCKETn Interrupt Mask Register(Sn_IMR).
BRDY[3:0]
O
Buffer Ready Indicator
These PIN are configured with SOCKET number, memory Type, and
buffer depth by user. When TX free or RX received size of the specified
SOCKET is same or greater than the configured buffer depth, these PIN
signals asserts high or low.
Refer to Pn_BRDYR & Pn_DPTHR
in “4.3 COMMON Registers”.



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