STMIPID02 datasheet(10/50 Pages) STMICROELECTRONICS

10 / 50 page

Ball assignment and description

Figure 7. Ball assignment: bottom view (49 balls)

DATA1P2

VDDIN_LDO

CLKP1

DATA1N2

DATA2P1

DATA1P1

DATA1N1

TDO

D10

LDO_TST

TCK

GNDE_LDO

DATA2N1

CLKP2

CLKN2

CLKN1

VDDOUT_LDO

VDDE_1V8

GNDE

TDI

TMS

XSDN

HSYNC

VDD_1V2

POR_SGN

VDDE_1V8

ERROR

INT

PCLK

GND_1V2

D11

GNDE

VSYNC

SCL

SDA

GNDE

POR_TST

EXTCLK

GND_PHY

Note:

The CSI-2 clock lanes must be in the middle of the two data lanes.

Note:

The PCLK, HSYNC, VSYNC must be routed in the middle of the output data bus for skew management reasons.

Table 3. Ball description

Ball name

Type

Description

Power supplies

VDDE_1V8

Power

1V8 digital IO supply

VDDIN_LDO

Power

1V8 voltage regulator supply

VDD_1V2

Power

1V2 MIPI D-PHY and digital core supply

GNDE

Ground

Digital IO ground

GNDE_LDO

Ground

Voltage regulator ground

GND_PHY

Ground

D-PHY ground

GND_1V2

Ground

Digital core ground

System interface

EXTCLK

Input

System clock input (for I2C slave), 6.0

MHz - 27.0 MHz

ERROR

Output

Error interrupt, indicates that an error

(either D-PHY or protocol) has occurred

INT

Output

MIPI CSI-2 short packet received

interrupt, indicates that a short packet

has been received

STMIPID02

Ball assignment and description

DS12803 - Rev 1

page 10/50

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