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131 / 152 page  Refresh Requirements Parameters Table 90: Refresh Requirement Parameters (Per Density) Parameter Symbol 64Mb 128Mb 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb Unit Number of banks 44448888 Refresh window: TCASE ≤ 85˚ tREFW 32 32 32 32 32 32 32 32 ms Refresh window: 85˚C < TCASE ≤ 105˚C tREFW 88888888 ms Required number of REFRESH commands (MIN) R 2048 2048 4096 4096 4096 8192 8192 8192 Average time be- tween REFRESH com- mands (for reference only) TCASE ≤ 85˚C REFab tREFI 15.6 15.6 7.8 7.8 7.8 3.9 3.9 3.9 μs REFpb tREFIpb (REFpb not supported below 1Gb) 0.975 0.4875 0.4875 0.4875 μs Refresh cycle time tRFCab 90 90 90 90 130 130 130 210 ns Per-bank REFRESH cycle time tRFCpb na 60 60 60 90 ns Burst REFRESH window = 4 × 8 × tRFCab tREFBW 2.88 2.88 2.88 2.88 4.16 4.16 4.16 6.72 μs AC Timing Table 91: AC Timing Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul- tiples of tCK) as well as the timing specifications when values for both are indicated. Parameter Symbol Min/ Max tCK Min Data Rate Unit Notes 1066 933 800 667 533 400 333 Maximum frequency – – 533 466 400 333 266 200 166 MHz Clock Timing Average clock period tCK(avg) MIN – 1.875 2.15 2.5 3 3.75 5 6 ns MAX – 100 100 100 100 100 100 100 Average HIGH pulse width tCH(avg) MIN – 0.45 0.45 0.45 0.45 0.45 0.45 0.45 tCK (avg) MAX – 0.55 0.55 0.55 0.55 0.55 0.55 0.55 Average LOW pulse width tCL(avg) MIN – 0.45 0.45 0.45 0.45 0.45 0.45 0.45 tCK (avg) MAX – 0.55 0.55 0.55 0.55 0.55 0.55 0.55 Absolute clock period tCK(abs) MIN – tCK(avg)min ± tJIT(per)min ps Absolute clock HIGH pulse width (with allowed jitter) tCH(abs), allowed MIN – 0.43 0.43 0.43 0.43 0.43 0.43 0.43 tCK (avg) MAX – 0.57 0.57 0.57 0.57 0.57 0.57 0.57 Absolute clock LOW pulse width (with allowed jitter) tCL(abs), allowed MIN – 0.43 0.43 0.43 0.43 0.43 0.43 0.43 tCK (avg) MAX – 0.57 0.57 0.57 0.57 0.57 0.57 0.57 Clock period jitter (with supported jitter) tJIT(per), allowed MIN – -90 -95 -100 -110 -120 -140 -150 ps MAX – 90 95 100 110 120 140 150 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Refresh Requirements Parameters 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 131 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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