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EDB8164B4PR-1DITF-R bảng dữ liệu(HTML) 133 Page - Micron Technology |
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133 / 152 page  Table 91: AC Timing (Continued) Notes 1–2 apply to all parameters and conditions. AC timing parameters must satisfy the tCK minimum conditions (in mul- tiples of tCK) as well as the timing specifications when values for both are indicated. Parameter Symbol Min/ Max tCK Min Data Rate Unit Notes 1066 933 800 667 533 400 333 Calibration RESET time tZQRESET MIN 3 50 50 50 50 50 50 50 ns READ Parameters3 DQS output access time from CK_t/CK_c tDQSCK MIN – 2500 2500 2500 2500 2500 2500 2500 ps MAX – 5500 5500 5500 5500 5500 5500 5500 DQSCK delta short tDQSCKDS MAX – 330 380 450 540 670 900 1080 ps 4 DQSCK delta medium tDQSCKDM MAX – 680 780 900 1050 1350 1800 1900 ps 5 DQSCK delta long tDQSCKDL MAX – 920 1050 1200 1400 1800 2400 – ps 6 DQS-DQ skew tDQSQ MAX – 200 220 240 280 340 400 500 ps Data-hold skew factor tQHS MAX – 230 260 280 340 400 480 600 ps DQS output HIGH pulse width tQSH MIN – tCH(abs) - 0.05 tCK (avg) DQS output LOW pulse width tQSL MIN – tCL(abs) - 0.05 tCK (avg) Data half period tQHP MIN – MIN (tQSH, tQSL) tCK (avg) DQ/DQS output hold time from DQS tQH MIN – tQHP - tQHS ps READ preamble tRPRE MIN – 0.9 0.9 0.9 0.9 0.9 0.9 0.9 tCK (avg) 7 READ postamble tRPST MIN – tCL(abs) - 0.05 tCK (avg) 8 DQS Low-Z from clock tLZ(DQS) MIN – tDQSCK (MIN) - 300 ps DQ Low-Z from clock tLZ(DQ) MIN – tDQSCK(MIN) - (1.4 × tQHS(MAX)) ps DQS High-Z from clock tHZ(DQS) MAX – tDQSCK (MAX) - 100 ps DQ High-Z from clock tHZ(DQ) MAX – tDQSCK(MAX) + (1.4 × tDQSQ(MAX)) ps WRITE Parameters3 DQ and DM input hold time (VREF based) tDH MIN – 210 235 270 350 430 480 600 ps DQ and DM input setup time (VREF based) tDS MIN – 210 235 270 350 430 480 600 ps DQ and DM input pulse width tDIPW MIN – 0.35 0.35 0.35 0.35 0.35 0.35 0.35 tCK (avg) Write command to first DQS latch- ing transition tDQSS MIN – 0.75 0.75 0.75 0.75 0.75 0.75 0.75 tCK (avg) MAX – 1.25 1.25 1.25 1.25 1.25 1.25 1.25 tCK (avg) DQS input high-level width tDQSH MIN – 0.4 0.4 0.4 0.4 0.4 0.4 0.4 tCK (avg) 216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM AC Timing 09005aef85eb530a 216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN 133 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved. |
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