EDB8164B4PR-1DITF-R datasheet(128/152 Pages) MICRON

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Table 88: Definitions and Calculations (Continued)

Symbol

Description

Calculation

Notes

tJIT(duty)

Defined with absolute and average specifications

for tCH and tCL, respectively.

tJIT(duty),min =

MIN((tCH(abs),min – tCH(avg),min),

(tCL(abs),min – tCL(avg),min)) × tCK(avg)

tJIT(duty),max =

MAX((tCH(abs),max – tCH(avg),max),

(tCL(abs),max – tCL(avg),max)) × tCK(avg)

Notes:

1. Not subject to production testing.

2. Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value.

tCK(abs), tCH(abs), and tCL(abs)

These parameters are specified with their average values; however, the relationship be-

tween the average timing and the absolute instantaneous timing (defined in the follow-

ing table) is applicable at all times.

Table 89: tCK(abs), tCH(abs), and tCL(abs) Definitions

Parameter

Symbol

Minimum

Unit

Absolute clock period

tCK(abs)

tCK(avg),min + tJIT(per),min

ps1

Absolute clock HIGH pulse width

tCH(abs)

tCH(avg),min + tJIT(duty),min2/tCK(avg)min

tCK(avg)

Absolute clock LOW pulse width

tCL(abs)

tCL(avg),min + tJIT(duty),min2/tCK(avg)min

tCK(avg)

Notes:

1. tCK(avg),min is expressed in ps for this table.

2. tJIT(duty),min is a negative value.

Clock Period Jitter

The LPDDR2 device can tolerate some clock period jitter without core timing parameter

derating. This section describes device timing requirements with clock period jitter

(tJIT(per)) in excess of the values found in the AC Timing section. Calculating cycle time

derating and clock cycle derating are also described.

Clock Period Jitter Effects on Core Timing Parameters

Core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR, tRC, tRAS, tRRD, tFAW) ex-

tend across multiple clock cycles. Clock period jitter impacts these parameters when

measured in numbers of clock cycles. Within the specification limits, the device is char-

acterized and verified to support tnPARAM = RU[tPARAM/tCK(avg)]. During device op-

eration where clock jitter is outside specification limits, the number of clocks or

tCK(avg), may need to be increased based on the values for each core timing parameter.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Clock Period Jitter

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

128

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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