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MMPF0200Z bảng dữ liệu(PDF) 90 Page - NXP Semiconductors |
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MMPF0200Z bảng dữ liệu(HTML) 90 Page - NXP Semiconductors |
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90 / 118 page  Analog Integrated Circuit Device Data 90 Freescale Semiconductor PF0200Z Functional Block Requirements and Behaviors Control Interface I2C Block Description A full description of all interrupt, mask, and sense registers is provided in Tables 101 to 112. SW2FAULTI SW2FAULTM SW2FAULTS Regulator 2 overcurrent limit Sense is 1 if above current limit L to H 8.0 SW3AFAULTI SW3AFAULTM SW3AFAULTS Regulator 3A overcurrent limit Sense is 1 if above current limit L to H 8.0 SW3BFAULTI SW3BFAULTM SW3BFAULTS Regulator 3B overcurrent limit Sense is 1 if above current limit L to H 8.0 SWBSTFAULTI SWBSTFAULTM SWBSTFAULTS SWBST overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN1FAULTI VGEN1FAULTM VGEN1FAULTS VGEN1 overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN2FAULTI VGEN2FAULTM VGEN2FAULTS VGEN2 overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN3FAULTI VGEN3FAULTM VGEN3FAULTS VGEN3 overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN4FAULTI VGEN4FAULTM VGEN4FAULTS VGEN4 overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN5FAULTI VGEN5FAULTM VGEN1FAULTS VGEN5 overcurrent limit Sense is 1 if above current limit L to H 8.0 VGEN6FAULTI VGEN6FAULTM VGEN6FAULTS VGEN6 overcurrent limit Sense is 1 if above current limit L to H 8.0 OTP_ECCI OTP_ECCM OTP_ECCS 1 or 2 bit error detected in OTP registers Sense is 1 if error detected L to H 8.0 Notes 68. Debounce timing for the falling edge can be extended with PWRONDBNC[1:0]. Table 101. Register INTSTAT0 - ADDR 0x05 Name Bit # R/W Default Description PWRONI 0 R/W1C 0 Power on interrupt bit LOWVINI 1 R/W1C 0 Low-voltage interrupt bit THERM110I 2 R/W1C 0 110 °C Thermal interrupt bit THERM120I 3 R/W1C 0 120 °C Thermal interrupt bit THERM125I 4 R/W1C 0 125 °C Thermal interrupt bit THERM130I 5 R/W1C 0 130 °C Thermal interrupt bit UNUSED 7:6 – 00 Unused Table 102. Register INTMASK0 - ADDR 0x06 Name Bit # R/W Default Description PWRONM 0 R/W1C 1 Power on interrupt mask bit LOWVINM 1 R/W1C 1 Low-voltage interrupt mask bit THERM110M 2 R/W1C 1 110 °C Thermal interrupt mask bit THERM120M 3 R/W1C 1 120 °C Thermal interrupt mask bit Table 100. Interrupt, Mask and Sense Bits (continued) Interrupt Mask Sense Purpose Trigger Debounce Time (ms) |
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