56F8335 datasheet(26/160 Pages) FREESCALE

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56F8335 Technical Data, Rev. 1

Freescale Semiconductor

Preliminary

PHASEB1

(TB1)

(MOSI1)

(GPIOC1)

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

Tri-stated

Input

Phase B1 — Quadrature Decoder 1, PHASEB input for decoder

TB1 — Timer B, Channel 1

SPI 1 Master Out/Slave In — This serial data pin is an output

from a master device and an input to a slave device. The master

device places data on the MOSI line a half-cycle before the clock

edge the slave device uses to latch the data. To activate the SPI

function, set the PHSB_ALT bit in the SIM_GPS register. For

details, see Part 6.5.8.

Port C GPIO — This GPIO pin can be individually programmed

as an input or output pin.

In the 56F8335, the default state after reset is PHASEB1.

In the 56F8135, the default state is not one of the functions

offered and must be reconfigured.

To deactivate the internal pull-up resistor, clear bit 1 in the

GPIOC_PUR register.

INDEX1

(TB2)

(MISO1)

(GPIOC2)

Schmitt

Input

Schmitt

Input/

Output

Schmitt

Input/

Output

Schmitt

Input/

Output

Input

Index1 — Quadrature Decoder 1, INDEX input

TB2 — Timer B, Channel 2

SPI 1 Master In/Slave Out — This serial data pin is an input to a

master device and output from a slave device. The MISO line of

a slave device is placed in the high-impedance state if the slave

device is not selected. The slave device places data on the

MISO line a half-cycle before the clock edge the master device

uses to latch the data. To activate the SPI function, set the

INDEX_ALT bit in the SIM_GPS register. See Part 6.5.8 for

details.

Port C GPIO — This GPIO pin can be individually programmed

as an input or output pin.

In the 56F8335, the default state after reset is INDEX1.

In the 56F8135, the default state is not one of the functions

offered and must be reconfigured.

To deactivate the internal pull-up resistor, clear bit 2 in the

GPIOC_PUR register.

Table 2-2 Signal and Package Information for the 128-Pin LQFP

Signal

Name

Pin No.

Type

State

During

Reset

Signal Description

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